Abstract: A semiconductor device includes a semiconductor layer disposed at a substrate and a plurality of active cells disposed at the semiconductor layer. Each active cell includes a trench extending into the semiconductor layer and a body region disposed in the semiconductor layer adjacent to a sidewall of the trench and at a first depth below the surface of the semiconductor layer. The semiconductor device further includes a termination cell disposed at the semiconductor layer adjacent to an edge of the plurality of active cells. The termination cell includes a trench extending into the semiconductor layer, and further includes a body region disposed in the semiconductor layer adjacent to a sidewall of the trench of the termination cell and at a second depth less than the first depth. The body regions of the active cells and of the termination cell have a conductivity type different than that of the semiconductor layer.

Abstract: In an embodiment, a method for processing instructions in a microcontroller is disclosed. In the embodiment, the method involves, upon receipt of an interrupt while an instruction is being executed, completing execution of the instruction by a shadow functional unit and, upon servicing the interrupt, terminating re-execution of the instruction and updating a main register file with the result of the execution of the instruction by the shadow functional unit.

Abstract: A microprocessor system is disclosed that includes a first data cache that is shared by a first group of one or more program threads in a multi-thread mode and used by one program thread in a single-thread mode. A second data cache is shared by a second group of one or more program threads in the multi-thread mode and is used as a victim cache for the first data cache in the single-thread mode.

Abstract: A device and method for encoding bits to symbols for a communication system are described. In one embodiment, a method for encoding bits to symbols for a communication system includes receiving a set of N-bit data to be transmitted, where N is an integer, generating side scrambling values using a polynomial, scrambling the set of N-bit data using the side scrambling values to produce scrambled data, mapping the scrambled data to a particular set of M symbols from a plurality of sets of M symbols, where M is an integer and M is smaller than N, and outputting the particular set of M symbols for transmission over a transmission medium. Other embodiments are also described.

Abstract: An RF circuit for providing phase coherent signals, an RF heating apparatus comprising the RF circuit and a method for providing phase coherent signals in an RF circuit. The RF circuit has a first frequency synthesiser including a fractional-N phase locked loop and a second frequency synthesiser including an integer-N phase locked loop. An output of the first frequency synthesiser is connected to a phase frequency detector of the integer-N phase locked loop of the second frequency synthesiser via a synchronization signal divider for distributing a synchronization signal from the first frequency synthesiser to the second frequency synthesiser. The integer-N phase locked loop of the second frequency synthesiser comprises a frequency divider of the same modulus as the synchronization signal divider.

Abstract: A digital to analog converter including a current source for providing a master current, a first sub digital to analog converter coupled to the current source which generates a plurality of currents, and a second sub digital to analog converter coupled to at least one of the plurality of currents from the first sub digital to analog converter which generates a second plurality of currents. The digital to analog converter also includes an overlap adjustment circuit coupled with the second sub digital to analog converter which adds current. The digital to analog converter is configured to operate in a first mode for generating a sine wave with a first bit level accuracy and, when in the first mode, the overlap adjustment circuit adds no current.

Abstract: A resistive non-volatile memory cell is programmed. A programming voltage is applied to a first terminal of the resistive non-volatile memory cell. Sensing, during the applying the programming voltage, determines if the resistive non-volatile memory cell has been programmed. Current is limited through the resistive non-volatile memory cell to a first magnitude. After a predetermined time, if the sensing has not detected that the resistive non-volatile memory cell has been programmed, the current through the resistive non-volatile memory cell is limited to a second magnitude greater than the first magnitude. The resistive non-volatile memory cell is also erased.

Abstract: A differential dynamic charge pump circuit comprising; a first charging stage in series with a second charging stage; the first charging stage comprising a first circuit input for receiving an alternating clock signal; a second circuit input for receiving an inverted version of the alternating clock signal; a first output inverter arrangement configured to receive output voltages from upper and lower charge pump arrangements and having a first output and a second output for providing a dynamic differential output; the second charging stage comprising a first input and a second input configured to receive the output signal from the first stage; a second output inverter arrangement configured to receive output voltages from upper and lower charge pump arrangements and having a first output and a second output for providing a dynamic differential output of the circuit.

Abstract: A solder ball pad for mounting a solder ball of a semiconductor device for preventing delamination of an overlying dielectric layer, and particularly devices and methods providing improved solder ball pad structures in a device such as a semiconductor device package.

Abstract: Electronic device packages and related fabrication methods are provided. An exemplary electronic device includes a semiconductor die having debug circuitry fabricated thereon, a framing structure including an interior portion having the semiconductor die mounted thereto, and a conductive element providing an electrical connection between the interior portion and a contact pad on the semiconductor die that corresponds or is otherwise coupled to an interface of the debug circuitry.

Abstract: An electronic device comprises one or more functional units, each functional unit being clocked by a respective clock signal. The electronic device further comprises a monitoring unit for providing a real-time estimate of an electrical current consumed by the functional units. The monitoring unit provides the real-time estimate on the basis of characteristic signals. The characteristic signals may comprise one or more of said clock signals, or one or more clock generating signals used to generate said clock signals. The electronic device may further comprise a power regulator responsive to the real-time estimate. A method of estimating in real-time an electrical current consumed by one or more functional units is also described.

Abstract: A sensor comprising a silicon substrate having a first and a second surface, integrated circuitry provided on the first surface of the silicon substrate, and a sensor structure provided on the second surface of the silicon substrate. The sensor structure and the integrated circuitry are electrically coupled to each other.

Abstract: A semiconductor package with an embedded capacitor and corresponding manufacturing methods are described. The semiconductor package with the embedded capacitor includes a semiconductor die having a first metal layer extending across at least a portion of a first side of the semiconductor die and a package structure formed on the first side of the semiconductor die. A first electrical conductor of the embedded capacitor is formed in the first metal layer of the semiconductor die. The package structure includes a second metal layer that has formed therein a second electrical conductor of the embedded capacitor. A dielectric of the embedded capacitor is positioned within either the semiconductor die or the package structure of the semiconductor package to isolate the first electrical conductor from the second electrical conductor of the embedded capacitor.

Abstract: The present disclosure provides embodiments for a semiconductor structure including a heat spreader that includes a graphene grid having a first major surface and a second major surface opposite the first major surface. The graphene grid has a plurality of holes, each hole having a first opening in the first major surface and a second opening in the second major surface. The heat spreader also includes a first copper portion covering the first major surface of the graphene grid, a second copper portion covering the second major surface of the graphene grid, and a plurality of copper vias filling the plurality of holes.

Abstract: A mechanism is provided to field adjust offset values for packaged sensors incorporated in devices. Embodiments provide for a processor in the sensor package to measure current environmental conditions and set a zero offset for the sensors in the package in light of those current environmental conditions. In this manner, any changes in the sensor over the sensor's lifetime and current environmental conditions that can affect functioning of the sensor can be accounted for in operational measurements taken by the device.

Abstract: The embodiments described herein provide calibration systems and methods for mixed-signal devices. Specifically, the embodiments provide systems and methods for calibrating mixed-signal devices that can facilitate effective calibration of such mixed-signal devices, including mixed-signal devices with poorly characterized nonlinearities that cannot be effectively calibrated with traditional calibration techniques. In general, the embodiments described herein calibrate by measuring output values from a mixed-signal device with a known calibration input values being applied. The measured output values are used to determine localized polynomial interpolants. Each of the determined localized polynomial interpolants is then evaluated at an uncorrected output value, and the evaluated localized polynomial interpolants are then used to generate correction values.

Abstract: A bias circuit for a transistor amplifier, the bias circuit comprising a low-pass filter block, a reference transistor, a sum node, a reference current source, and a current difference block, wherein the low-pass filter block is configured to sense a DC bias voltage at a control terminal of the transistor amplifier and provide the DC bias voltage to a control terminal of the reference transistor; the reference transistor is configured to output a bias current in response to the DC bias voltage and provide the bias current to the sum node; the sum node is configured to receive a reference current from the reference current source and combine the reference current with the bias current from the reference transistor to provide a difference current; and the current difference block is configured to receive the difference current from the sum node and provide the difference current to the control terminal of the transistor amplifier.

Abstract: A device for switchably routing down-converted radio frequency (RF) signals from a plurality of inputs to a plurality of outputs, and a method of operating the same. The device includes a respective switch for each output. The device also includes an interconnect arrangement. The interconnect arrangement includes a respective transmission line for each input. Each transmission line includes a plurality of branches for routing a down-converted RF signal received at the input of that transmission line to the switch of each output. The switch of each output is operable selectively to connect one of the transmission lines to its output. The interconnect arrangement also includes a plurality of cross-over points at which two of the branches cross over each other.

Abstract: A method of evaluating a capacitive interface including discharging the capacitive interface to a lower voltage, timing while applying a unit charge to the capacitive interface until a voltage of the capacitive interface rises to a reference voltage and determining a corresponding charge time value, charging the capacitive interface to an upper voltage that is greater than the reference voltage, and timing while removing the unit charge from the capacitive interface until a voltage of the capacitive interface falls to the reference voltage and determining a corresponding discharge time value. The charge and discharge time values may be used to evaluate the capacitive interface by determining capacitance and leakage current. The time values may be determined using a counter. A capacitive interface evaluation system for evaluating the capacitive interface may include a charge circuit, a comparator, a counter and a controller.

Abstract: A method for forming a semiconductor device includes forming a select gate over a substrate and forming a charge storage layer and a control gate over the select gate. The charge storage layer and control gate overlap a first sidewall of the select gate and the charge storage layer is between the select gate and the control gate. A protective spacer is formed, wherein the protective spacer has a first portion adjacent a first sidewall of the charge storage layer and on the substrate, and the protective spacer is thinned. After thinning the protective spacer, a sidewall spacer is formed over the protective spacer, wherein the sidewall spacer has a first portion on the substrate, and the first portion of the protective spacer is between the first sidewall of the control gate and the first portion of the sidewall spacer.