Patents Assigned to NXP
  • Remapping constant points in a white-box implementation
    Patent number: 9569639
    Abstract: A non-transitory machine-readable storage medium encoded with instructions for execution by a keyed cryptographic operation by a cryptographic system mapping an input message to an output message, wherein the cryptographic operation includes at least one round including a non-linear mapping function configured to map input data to output data, including: instructions for determining that the input data has a diversification number less than a diversification level threshold number; instructions for remapping the input data to a remapped input data, wherein the remapped input data corresponds to an input data having a diversification number greater than or equal to the diversification threshold value, and instructions for inputting the remapped input data into the non-linear mapping function to obtain output data.
    Type: Grant
    Filed: September 12, 2014
    Date of Patent: February 14, 2017
    Assignee: NXP B.V.
    Inventors: Wil Michiels, Jan Hoogerbrugge
  • RF power transistors with impedance matching circuits, and methods of manufacture thereof
    Patent number: 9571044
    Abstract: Embodiments of an RF amplifier include a transistor with a control terminal and first and second current carrying terminals, and a shunt circuit coupled between the first current carrying terminal and a ground reference node. The shunt circuit includes a first shunt inductance, a second shunt inductance, and a shunt capacitor coupled in series. The second shunt inductance and the shunt capacitor form a series resonant circuit in proximity to a center operating frequency of the amplifier, and an RF cold point node is present between the first and second shunt inductances. The RF amplifier also includes a video bandwidth circuit coupled between the RF cold point node and the ground reference node.
    Type: Grant
    Filed: October 21, 2015
    Date of Patent: February 14, 2017
    Assignee: NXP USA, INC.
    Inventors: Ning Zhu, Damon G. Holmes, Jeffrey K. Jones
  • Deep trench isolation structures and systems and methods including the same
    Patent number: 9570548
    Abstract: Deep trench isolation structures and systems and methods including the same are disclosed herein. The systems include a semiconductor device. The semiconductor device includes a semiconductor body, a device region, and the deep trench isolation structure. The deep trench isolation structure is configured to electrically isolate the device region from other device regions that extend within the semiconductor body. The deep trench isolation structure includes an isolation trench, a dielectric material that extends within the isolation trench, a first semiconducting region, and a second semiconducting region. The methods include methods of operating an integrated circuit device that includes a plurality of semiconductor devices that include the disclosed deep trench isolation structures.
    Type: Grant
    Filed: August 20, 2015
    Date of Patent: February 14, 2017
    Assignee: NXP USA, INC.
    Inventors: Xu Cheng, Daniel J. Blomberg, Jiang-Kai Zuo
  • Three-dimensional integrated circuit systems in a package and methods therefor
    Patent number: 9570387
    Abstract: A method for making a packaged semiconductor device includes dispensing a first adhesive into a first cavity of a substrate having a first major surface and a second major surface. The first cavity extends into the substrate from the second major surface. The method further includes placing a first component having a thickness less than a thickness of the substrate into the first cavity such that the first adhesive physically contacts a first major surface of the first component and at least partially fills a gap between sidewalls of the first component and sidewalls of the first cavity. After placing the first component, a second major surface of the first component is coplanar with the second major surface of the substrate.
    Type: Grant
    Filed: August 19, 2015
    Date of Patent: February 14, 2017
    Assignee: NXP USA, Inc.
    Inventors: Zhiwei Gong, Scott M. Hayes, Michael B. Vincent
  • Autonomous power supply
    Patent number: 9570941
    Abstract: Aspects of the present disclosure are directed to providing power from two or more power sources. As may be implemented in accordance with one or more embodiments, a switching circuit includes a switching transistor connected between a backup power supply and both a primary power supply and an internal power rail. When power is provided via the primary power supply, the switching circuit operates in a blocking state in which back current is prevented from flowing to the backup power supply while the primary power supply couples power to the internal power rail. When the primary power supply is disconnected or interrupted, a voltage coupled to a gate/control terminal of the switching circuit drops and the switching circuit automatically switches to another state in which the internal power rail is powered by the backup power supply.
    Type: Grant
    Filed: October 31, 2014
    Date of Patent: February 14, 2017
    Assignee: NXP B.V.
    Inventor: Madan Vemula
  • Frequency synthesizer circuit
    Patent number: 9571071
    Abstract: The invention relates to frequency synthesizer circuits, and in particular to frequency synthesizer circuits characterized by a small channel spacing. Embodiments disclosed include a frequency synthesizer circuit for a radio receiver, the circuit comprising: a digitally controlled oscillator configured to generate an output signal with an output frequency on application of an oscillator enable signal; a delay module; configured to delay an input reference signal to generate a delayed reference signal; and a duty cycle module configured to modulate the oscillator enable signal based on a period of an input reference signal and the delay of the delayed reference signal, such that a ratio between the output frequency and the frequency of the input reference signal is a non-integer.
    Type: Grant
    Filed: June 23, 2015
    Date of Patent: February 14, 2017
    Assignee: NXP B.V.
    Inventors: Tarik Saric, Salvatore Drago
  • Multimode rake receiver, cellular base station and cellular communication device
    Patent number: 9572199
    Abstract: A multimode rake receiver comprise a common antenna interface, arranged to at least receive in a first mode a first CDMA radio channel carrying information encoded according to a first baseband modulation standard and to receive in a second mode a second CDMA radio channel carrying information encoded according to a second baseband modulation standard; and a common signal processing path, at least arranged to process in the first mode the first CDMA radio channel and in the second mode the second CDMA radio channel, wherein the common signal path comprises a common descrambling and de-spreading unit and a common hybrid code generating unit arranged to provide to the common descrambling and de-spreading unit chip codes applicable in the first mode to the first CDMA radio channel and in the second mode to the second CDMA radio channel.
    Type: Grant
    Filed: October 19, 2011
    Date of Patent: February 14, 2017
    Assignee: NXP USA, INC.
    Inventors: Guy Drory, Eliya Babitsky, Ron Bercovich
  • Semiconductor device and driver circuit with an active device and isolation structure interconnected through a diode circuit, and method of manufacture thereof
    Patent number: 9570440
    Abstract: Embodiments of semiconductor devices and driver circuits include a semiconductor substrate having a first conductivity type, an isolation structure (including a sinker region and a buried layer), an active device within area of the substrate contained by the isolation structure, and a diode circuit. The buried layer is positioned below the top substrate surface, and has a second conductivity type. The sinker region extends between the top substrate surface and the buried layer, and has the second conductivity type. The active device includes a body region of the second conductivity type, and the diode circuit is connected between the isolation structure and the body region. The diode circuit may include one or more Schottky diodes and/or PN junction diodes. In further embodiments, the diode circuit may include one or more resistive networks in series and/or parallel with the Schottky and/or PN diode(s).
    Type: Grant
    Filed: September 21, 2015
    Date of Patent: February 14, 2017
    Assignee: NXP USA, Inc.
    Inventors: Weize Chen, Hubert M. Bode, Richard J. De Souza, Patrice M. Parris
  • Semiconductor device having a plurality of source lines being laid in both X and Y directions
    Patent number: 9570605
    Abstract: A device is disclosed. The device includes a semiconductor substrate, a plurality of source lines formed on a surface of the semiconductor substrate. The plurality of source lines are laid in both X and Y directions. The device further includes a plurality of gate lines laid out over source lines in X direction in the plurality of source lines, a source contact line that connects source lines in the plurality of source lines that are terminating in Y direction, a gate contact line that connects the plurality of gate lines and a drain contact.
    Type: Grant
    Filed: May 9, 2016
    Date of Patent: February 14, 2017
    Assignee: NXP B.V.
    Inventor: Steven Thomas Peake
  • INTEGRATED CIRCUIT DEVICE AND METHOD FOR APPLYING ERROR CORRECTION TO SRAM MEMORY
    Publication number: 20170039104
    Abstract: In accordance with an embodiment of the invention, an integrated circuit (IC) device is disclosed. In the embodiment, the IC device includes an SRAM module, wrapper logic coupled to the SRAM module, a context source, and an ECC profile controller coupled to the context source and to the wrapper logic, the ECC profile controller configured to select an ECC profile in response to context information received from the context source for use by the wrapper logic.
    Type: Application
    Filed: August 6, 2015
    Publication date: February 9, 2017
    Applicant: NXP B.V.
    Inventors: Ajay Kapoor, Nur Engin, Steven Thoen, Jose Pineda de Gyvez
  • INTEGRATED CIRCUIT DEVICE AND METHOD FOR READING DATA FROM AN SRAM MEMORY
    Publication number: 20170039102
    Abstract: In accordance with an embodiment of the invention, an IC device is disclosed. In the embodiment, the IC device includes an array of bit cells of static random-access memory (SRAM), a multi-level digitization module configured to generate a value in a range of values from a bit cell in the array of bit cells, the range of values including more than two discrete values, an output buffer configured to store the generated values, and an error correction code (ECC) decoder configured to output error corrected values based on the stored values.
    Type: Application
    Filed: August 6, 2015
    Publication date: February 9, 2017
    Applicant: NXP B.V.
    Inventors: Nur Engin, Ajay Kapoor
  • INTEGRATED CIRCUIT DEVICE AND METHOD FOR REDUCING SRAM LEAKAGE
    Publication number: 20170039103
    Abstract: An integrated circuit (IC) device including an SRAM module coupled to wrapper logic is disclosed. The wrapper logic includes an error correction code (ECC) encoder configured to encode input data in accordance with an ECC encoding scheme and output the encoded input data to the SRAM module, an ECC decoder configured to decode output data received from the SRAM module, output the decoded output data, and write decoding information back to the SRAM module, an error controller coupled to the ECC decoder that is configured to control the ECC decoder in accordance with the ECC encoding scheme, and a central controller coupled to the components of the wrapper logic and the SRAM module in order to control operations between the components of the wrapper logic and the SRAM module.
    Type: Application
    Filed: August 6, 2015
    Publication date: February 9, 2017
    Applicant: NXP B.V.
    Inventors: Nur Engin, Ajay Kapoor
  • Cut-through forwarding module and a method of receiving and transmitting data frames in a cut-through forwarding mode
    Patent number: 9565137
    Abstract: The disclosure relates to cut-through forwarding module, an integrated circuit, a semiconductor device and a method of receiving and transmitting data frames in a cut-through forwarding mode. The cut-through forwarding module processes received data frames in data blocks. The module comprises a pre-loading unit for storing a first data block of a received data frame. The stored first data block may be pre-loaded by the pre-loading unit in a transmitter unit before a receiver unit receives a subsequent data frame. The processing unit controls the transfer of a first data block to the pre-loading unit and controls the use of a pre-loaded data block as a first data block of a data frame to be transmitted.
    Type: Grant
    Filed: April 26, 2012
    Date of Patent: February 7, 2017
    Assignee: NXP USA, Inc.
    Inventor: Graham Edmiston
  • Systems and methods for managing task watchdog status register entries
    Patent number: 9563494
    Abstract: The present disclosure provides system and method embodiments for a status register comprising a plurality of bits, where each of the plurality of bits of the status register is associated with one of a plurality of entities. A trigger mechanism is configured to write a trigger data pattern to the status register, where the trigger data pattern comprises a first state value for each of the plurality of bits of the status register. A capture mechanism is configured to write a second state value to each bit of the status register that is associated with an entity that is presently associated with a first type of entity status information, in response to a detection that the trigger data pattern is written to the status register.
    Type: Grant
    Filed: March 30, 2015
    Date of Patent: February 7, 2017
    Assignee: NXP USA, Inc.
    Inventors: William C. Moyer, Michael Kardonik
  • Method of generating a structure and corresponding structure
    Patent number: 9563754
    Abstract: Disclosed is a method of generating a structure comprising at least one virtual machine, the method comprising: obfuscating a first virtual machine source code, thereby yielding a first obfuscated virtual machine (OVM) source code; associating a processor identifier with the first OVM source code, thereby yielding a processor-specific first OVM source code; compiling the processor-specific first OVM source code, thereby yielding a processor-specific first OVM. Furthermore, a structure generated by said method is disclosed.
    Type: Grant
    Filed: November 20, 2014
    Date of Patent: February 7, 2017
    Assignee: NXP B.V.
    Inventors: Vincent Cedric Colnot, Peter Maria Franciscus Rombouts, Philippe Teuwen, Frank Michaud
  • High voltage failure recovery for emulated electrically erasable (EEE) memory system
    Patent number: 9563491
    Abstract: The present disclosure provides methods and circuits for managing failing sectors in a non-volatile memory. A record address and a read control signal are received, where the record address identifies a location in the non-volatile memory. The record address is compared with a plurality of dead sector addresses, where the dead sector addresses correspond to a subset of sectors located in the non-volatile memory. Data located at the record address is determined to be invalid in response to a combination of a first detection that the record address matches one of the dead sector addresses and a second detection that the read control signal indicates a read operation is requested to be performed on the non-volatile memory.
    Type: Grant
    Filed: September 12, 2014
    Date of Patent: February 7, 2017
    Assignee: NXP USA, Inc.
    Inventors: Ross S. Scouller, Jeffrey C. Cunningham, Daniel L. Andre, Tim J. Coots
  • Broadband radio frequency power amplifiers, and methods of manufacture thereof
    Patent number: 9564861
    Abstract: An embodiment of an amplifier has a bandwidth defined by low and upper cutoff frequencies. The amplifier includes an input impedance matching circuit and a transistor. The transistor has a gate, a first current conducting terminal coupled to an output of the amplifier, and a second current conducting terminal coupled to a reference node. The input impedance matching circuit has a filter input coupled to an input of the amplifier, a filter output coupled to the gate of the transistor, and a multiple pole filter coupled between the filter input and the filter output. A first pole of the filter is positioned at a first frequency within the bandwidth, and a second pole of the filter is positioned at a second frequency outside the bandwidth. The input impedance matching circuit is configured to filter the input RF signal to produce a filtered RF signal at the filter output.
    Type: Grant
    Filed: October 31, 2014
    Date of Patent: February 7, 2017
    Assignee: NXP USA, INC.
    Inventors: Lei Zhao, Jeffrey K. Jones, Basim H. Noori, Michael E. Watts
  • Shock sensor with latch mechanism and method of shock detection
    Patent number: 9562825
    Abstract: A micromechanical shock sensor includes a proof mass coupled to a surface of a substrate and a projection element extending laterally from the proof mass. The shock sensor further includes a latch mechanism and a retention anchor. The latch mechanism has a latch spring attached to the surface and a latch tip extending from a movable end of the latch spring. The retention anchor is attached to the surface and is located proximate the latch tip. The proof mass is configured for planar movement relative to the substrate when the proof mass is subjected to a force of at least a threshold magnitude. Movement of the proof mass in response to the force causes the latch tip to become retained between the projection element and the retention anchor to place the shock sensor in a latched state. The latched state may be detected by optical inspection, probe, or external readout.
    Type: Grant
    Filed: November 7, 2014
    Date of Patent: February 7, 2017
    Assignee: NXP USA, Inc.
    Inventor: Michael Naumann
  • 3-level bridge driver with single supply and low common mode EMI emission
    Patent number: 9564948
    Abstract: In one embodiment, a circuit, having a single supply, is provided to transmit a wireless signal with low common mode electromagnetic interference (EMI) emission. The circuit can achieve common mode attenuations of 40 dB or greater as a result of the symmetric built circuit. Also included is a system that includes a transmission circuit and a receiver circuit, and a method of using such a system.
    Type: Grant
    Filed: November 18, 2011
    Date of Patent: February 7, 2017
    Assignee: NXP B.V.
    Inventors: Siegfried Arnold, Robert Kofler, Davide Maschera, Bardo Mueller
  • Devices with arbitrated interface busses, and methods of their operation
    Patent number: 9563590
    Abstract: A system having an arbitrated interface bus and a method of operating the same are provided. The system may include, but is not limited to, one or more registers configured to store data, a plurality of external interfaces configured to receive data access requests for the register(s), an arbitrator communicatively coupled to each of the plurality of external interfaces, and an interface bus communicatively coupled between the arbitrator and the register(s), wherein the arbitrator is configured to arbitrate control of the interface bus between the plurality of external interfaces.
    Type: Grant
    Filed: March 17, 2014
    Date of Patent: February 7, 2017
    Assignee: NXP USA, INC.
    Inventors: Joseph S. Vaccaro, Michael P. Collins