Abstract: A self-powered gate drive circuit comprising a first capacitor electrically coupled to a power semiconductor collector node of the circuit; a first switch arranged between the first capacitor and a second capacitor, the first switch electrically coupling the first and second capacitors when switched on; the second capacitor; a first diode, the first diode anode electrically coupled to the first capacitor and the first diode cathode electrically coupled to the first switch; a second diode, the second diode cathode electrically coupled to the first capacitor and the second diode anode electrically coupled with a ground node of the circuit; and a second switch, wherein the second switch electrically couples the second capacitor with a power semiconductor gate node when switched on.

Abstract: An interrupt supervision system comprises an interrupt controller device comprising a plurality of interrupt request input lines and at least one output line connectable to a processing device.

Abstract: A method of obscuring software code including a plurality of instructions, comprising: determining, by a processor, a number N prior instructions to a current instruction; encoding the current instruction based upon a first function, a second function, and the N prior instructions, wherein the second function is based upon the N prior instructions, and wherein the first function is based upon the current instruction and an output of the second function.

Abstract: Test control point insertion and x-bounding for Logic Built-In Self-Test (LBIST) using observation circuitry. In some embodiments, LBIST circuitry may include a plurality of test control circuits coupled to a scan chain of a Circuit Under Test (CUT), and a plurality of observation circuits coupled to the test control circuits, each of the plurality of observation circuits including one or more latch devices configured to drive a respective one of the plurality of test control circuits. In other embodiments, a method of testing an integrated circuit may include issuing an instruction that a plurality of observation circuits and a plurality of input/output (I/O) control circuits within the integrated circuit enter a test mode, and providing, one or more test patterns to a selected one or more of a plurality of scan chains within the integrated circuit and to each of the plurality of observation circuits.

Abstract: A device is described for operating a multi-partition networking system, the device comprising hardware resources for the operation of a primary partition for performing tasks, a primary buffer for holding packets for processing within a partition of the multi-partition system and a reserve buffer. The device is arranged to allocate the primary buffer for use by the primary partition and allocate the reserve buffer for use by the primary partition when at least a suspicious condition is detected in the primary partition. A method of operating a multi-partition networking system is also described.

Abstract: A radar transceiver is disclosed. The radar transceiver includes a computing unit, a sweep control unit, a set of transmitters for transmitting radar chirps to targets, a set of receivers for receiving reflected chirps from the targets, and a timing engine processor coupled to the set of transmitters and to the set of receivers and configured to transmit a first set of control signals. The timing engine processor receives a second set of control signals generated by the computing unit. The sweep control unit receives a first control signal and a second control signal from the timing engine processor. The first control signal indicating a start time of a chirp and the second control signal indicating a reset time for resetting the chirp. A controlled phased lock loop (PLL) generates a local oscillator signal which is inputted to transmitters and receivers.

Abstract: A method for configuring a via in a semiconductor device includes determining time dependent dielectric breakdown failure rate as a function of distance between the via and a metal line, generating candidate via configurations with different sizes, rotation, and offset values for the via, determining TDDB failure rate for the candidate via configurations, and selecting one of the candidate via configurations with an optimal TDDB failure rate for the via.

Abstract: Embodiments of a device and method are disclosed. In an embodiment, a flip-flop circuit is disclosed. The flip-flop circuit includes a master latch, a slave latch connected to the master latch, and a dual-function circuit connected between the master latch and the slave latch and configured to perform state retention and double sampling.

Abstract: A diode includes a semiconductor substrate having a surface; a first contact region disposed at the surface of the semiconductor substrate and having a first conductivity type; and a second contact region disposed at the surface, laterally spaced from the first contact region, and having a second conductivity type. The diode also includes a buried region disposed in the semiconductor substrate vertically adjacent to the first contact region, having the second conductivity type, and electrically connected with the second contact region; and an isolation region disposed at the surface between the first and second contact regions. The diode also includes a separation region disposed at the surface between the first contact region and the isolation region, the separation region formed from a portion of a first well region disposed in the semiconductor substrate that extends to the surface.

Abstract: A mechanism is provided for enhancing the sensitivity of an ion-sensitive semiconductor device by creating a second gate coupled to a sense plate that can improve the amount of charge brought to the ion-sensitive semiconductor device conductivity modulated region (e.g., a channel region of an ISFET). This is accomplished by utilizing a buried dielectric layer associated with the ion-sensitive semiconductor device conductivity modulated region as the second gate dielectric. The buried dielectric layer is coupled to the sense plate using an isolated well region as a conductor that is coupled to metal layers extending to the sense plate. Some embodiments further use the buried dielectric layer as the sole gate dielectric for the semiconductor device, thereby allowing the traditional gate dielectric region to be coupled to a protection diode. This protection diode then protects the gate dielectric from plasma induced damage and electrostatic discharge.

Abstract: A switch mode power converter configured for operation with a plurality of outputs is disclosed. The switch mode power converter includes an inductive element and a resistance in series with the inductive element. The resistance is series with the inductive element is used for determining a current through the inductive element. The resistance is a resistance between the main terminals of a switch in an on-state. The switch have two main terminals and a control terminal and being arranged for directing current through the inductive element to a one of the plurality of outputs.

Abstract: The embodiments described herein provide devices and methods to facilitate ripple control communication. Specifically, the embodiments provide devices and methods for decoding ripple control data from ripple signals, such as ripple signals that have been superimposed over power signals used to transmit power. These embodiments provide devices and methods that use band-pass filter, signal multiplier, fast and slow low-pass filters, and accumulate a difference between outputs of these slow and fast low-pass filters. This accumulated difference is then used to decode the ripple control data.

Abstract: There is provided a network node for use in a wireless sensor network, said network node being arranged to determine communication activities of the network node in different spatial directions extending from the network node, and said network node comprising at least one visual indicator being arranged to provide a visual indication of said communication activities. A wireless sensor network comprising such a network node is also disclosed, as is a method facilitating positioning a network node in a sensor network.

Abstract: Protection device structures and related fabrication methods are provided. An exemplary semiconductor protection device includes a base region of semiconductor material having a first conductivity type, an emitter region within the base region having the opposite conductivity type, and a collector region of semiconductor material having the second conductivity type, wherein at least a portion of the base region resides between the emitter region and the collector region. A depth of the collector region is greater than a depth of the emitter region and less than or equal to a depth of the base region such that a distance between a lateral boundary of the emitter region and a proximal lateral boundary of the collector region is greater than zero and the collector region does not overlap or otherwise underlie the emitter region.

Abstract: A memory controller comprises a connection interface connected or connectable to a memory. The memory controller is arranged to read data from the memory via the connection interface. The memory controller further comprises a clock unit arranged to provide a data transfer clock signal having a first frequency. The data transfer clock signal may be provided to the memory via the connection interface. The data transfer clock signal is arranged for clocking a data transfer from the memory to the memory controller via the connection interface as well as an oversampling circuit arranged to sample a calibration data pattern read by the memory controller via the connection interface at a second frequency to provide an over-sampled calibration data pattern. The second frequency is larger than the first frequency. The memory controller is arranged to determine a timing shift of a data transfer from the memory to the memory controller based on the oversampled calibration data pattern.

Abstract: Methods, systems and apparatus are provided to apply a magnetic pre-conditioning to magnetic tunneling junction (MTJ) sensors and other micro-magnetic devices after fabrication but before testing, trimming or other subsequent processing. The fabricated sensor device is passed through a magnetic field that has a known direction and orientation relative to the device so that the device is placed into a known state prior to final testing and trimming. Various embodiments allow the field to be applied in situ by a permanent magnet or electromagnet as the devices are being processed by a conventional device handler or similar processing system.

Abstract: A microelectromechanical systems (MEMS) device includes a structural layer having a top surface. The top surface includes surface regions that are generally parallel to one another but are offset relative to one another such that a stress concentration location is formed between them. Laterally propagating shallow surface cracks have a tendency to form in the structural layer, especially near the joints between the surface regions. A method entails fabricating the MEMS device and forming trenchesin the top surface of the structural layer of the MEMS device. The trenches act as a crack inhibition feature to largely prevent the formation of deep cracks in structural layer which might otherwise result in MEMS device failure.

Abstract: A multi-core system configured to execute a plurality of tasks and having a semaphore engine and a direct memory access (DMA) engine capable of selecting, by a task scheduler of a first core, a first task for execution by the first core. In response to a semaphore lock request, the task scheduler of the first core switches the first task to an inactive state and selects a next task for execution by the first core. After the semaphore engine acquires the semaphore lock of the first semaphore, a data transfer request is provided to the DMA engine. In response to the data transfer request, the DMA engine transfers data associated with the locked first semaphore to the entry of the workspace of the first core.

Abstract: Various exemplary embodiments relate to a method for detecting an object using radar system having M transmit antennas, N receive antennas, and a processor, including: receiving, by the processor, N×M digital signals, wherein the N receivers receive M received signals corresponding to M sequences of encoded transmitted signals resulting in N×M digital signals; processing the N×M digital signals to produce N×M first range/relative velocity matrices; applying a phase compensation to N×(M?1) first range/relative velocity matrices to compensate for a difference in range between the N×(M?1) first range/relative velocity matrices and the Mth range/velocity matrix; decoding the M phase compensated range/relative velocity matrices for the N receivers using an inverse of the transmit encoding to produce M decoded phase range/relative velocity matrices for the N receivers; detecting objects using the M range/relative velocity matrices for the N receivers to produce a detection vector.

Abstract: An electronic device has a runtime integrity checker for monitoring contents of storage locations in an address range. The runtime integrity checker has a location selector for selecting the storage locations by generating addresses within the address range for locations to be checked, an interface unit coupled to the location selector for receiving the addresses for accessing the locations to be checked via a bus interface, and a processor coupled to the interface unit for retrieving the contents from the locations to be checked. A mask unit is provided for processing a mask for defining the locations to be checked based on bits in the mask. The hardware enables selective monitoring of non contiguous storage locations or data areas.