Abstract: A communication station is suitable for contactless communication with transponders and with further communication stations and has a first protocol-executing circuit and a second protocol-executing circuit, the first protocol-executing circuit being designed to effect communication between the communication station and transponders under a station/transponder protocol and the second protocol-executing circuit being designed to effect communication between the communication station and further communication stations under a station/station protocol.

Abstract: A non-volatile memory device includes an array of non-volatile memory cells. A memory cell in the array of memory cells includes a first resistive element including a first terminal and a second terminal, a second resistive element including a first terminal and a second terminal, and a select transistor including a gate electrode coupled to a word line, a first current electrode coupled to the first terminal of the first resistive element and the first terminal of the second resistive element, and a second current electrode coupled to a bit line. The second terminal of the first resistive element is coupled to a first source line, and the second terminal of the second resistive element is coupled to a second source line.

Abstract: A system and method for monitoring a plurality of data streams is disclosed. At a first processing stage, a first memory area is associated to an element of a plurality of data streams. Upon arrival of a frame associated with one of the plurality of data streams, a second memory area is associated to the arrived frame based on the element. In the second memory area, a data indicating an arrival of the arrived frame is recorded and on a successful recording, the frame is forwarded to a second processing stage. An independent process executes at a preselected time interval to erase contents of the first memory area.

Abstract: A battery pack has first and second battery terminals, plural battery cells each with a battery element, a cell supervisor electrically connected to the battery element, and a communication section to communicate with the cell supervisor. The battery elements are connected serially between the first and second battery terminals. Bus interfaces are arranged in alternating fashion with the battery cells to define a daisy chain bus, each such bus interface being configured for signal communication, the interfaces respectively connecting the communication sections of two adjacent battery cells. A battery manager communicates with the battery cells via the daisy chain bus. The battery manager sends a command message to the battery cells using a through mode protocol, and each battery cell sends at least one of a confirmation message and a service request to the battery manager using a shift mode protocol.

Abstract: A dielectric layer is formed over the substrate in the capacitor region and the memory region and a select gate layer is formed over the dielectric layer. A select gate is formed over the memory region and a plurality of lines of electrodes over the capacitor region from the select gate layer. A charge storage layer is formed over the capacitor region and the memory region including over the select gate and the plurality of lines. A control gate layer is formed over the charge storage layer over the capacitor region and over the memory region. The control gate layer is patterned to form a control gate of a memory cell over the memory region and a first electrode of a capacitor over the capacitor region. The plurality of lines are connected to the capacitor region to form a second electrode of the capacitor.

Abstract: A method for forming a packaged semiconductor device includes attaching a first major surface of a semiconductor die to a plurality of protrusions extending from a package substrate. A top surface of each protrusion has a die attach material, and the plurality of protrusions define an open region between the first major surface of the semiconductor die and the package substrate. Interconnects are formed between a second major surface of the semiconductor die and the package substrate in which the second major surface opposite the first major surface. An encapsulant material is formed over the semiconductor die and the interconnects.

Abstract: A semiconductor device configured with one or more integrated breakdown protection diodes in non-isolated power transistor devices and electronic apparatus, and methods for fabricating the devices.

Abstract: A master slave storage circuit can include a first master portion coupled to a first master data storage node and a first slave portion coupled to a first slave data storage node. The first master portion can comprise one of a first master latch or a first master capacitive element coupled to the first master data storage node and the first slave portion comprises one of a first slave latch or a first slave capacitive element coupled to the first slave data storage node. If the first master portion comprises the first master latch, the first slave portion comprises the first slave capacitive element, and if the first master portion comprises the first master capacitive element, the first slave portion comprises the first slave latch.

Abstract: A DC-DC converter (100) includes a switching transistor (M0) connecting an input power terminal (VIN) to an inductor (114) that is also connected to an output power terminal (VOUT), a synchronous rectification transistor (M1) connected to a junction node (113) between the inductor (114) and the switching transistor (M0), and a synchronous rectifier control circuit (200) with an integration capacitor (226) having a voltage that is charged and discharged by first and second current sources (210, 220) to track the charging and discharging of the inductor current, thereby generating a synchronous rectifier control signal (SR) that is applied to the synchronous rectification transistor to discharge the inductor current to zero.

Abstract: A semiconductor device comprises a first contact layer, a first drift layer adjacent the first contact layer, a buried body layer adjacent the first drift layer and a second contact layer. A first vertical trench and a second vertical trench are provided, the first and second vertical trenches being spaced with respect to each other and extending from the second contact layer to substantially beyond the buried body layer. A second drift layer is also provided and sandwiched between the buried body layer and the second contact layer.

Abstract: A 3D graphics system uses encryption keys to decrypt received and stored texture tiles of a texture in accordance with received and stored texture tile status data which indicates whether a texture tiles is encrypted or not and which one of the encryption keys is used. The decrypted texture tiles are rendered and at least a plurality of the rendered tiles is encrypted. The encrypted rendered tiles are stored in a frame buffer. Buffer tile status data is stored which indicates whether a rendered tile is encrypted or not before storage in the frame buffer, and which one of the encryption keys has been used. The encrypted rendered tiles stored in the frame buffer are decrypted in accordance with the buffer tile status data.

Abstract: A data bus network interface module for enabling reception and transmission of application messages to/from at least one host processing module of an integrated digital signal processing device via a data bus network is described. The data bus network interface module being arranged to receive at least one data bus message from at least one remote network node via the data bus network, read an identifier field of the received at least one data bus message, and make data content of the received at least one data bus message available to at least one debug module if the identifier field comprises an identifier value defined for debug use.

Abstract: Semiconductor device structures and related fabrication methods are provided. An exemplary semiconductor device structure includes a body well region having a first conductivity type, a drift region and a source region each having a second conductivity type, where a channel portion of the body well region resides laterally between the source region and a first portion of the drift region that is adjacent to the channel portion. A gate structure overlies the channel portion and the adjacent portion of the drift region. A portion of the gate structure overlying the channel portion proximate the source region has the second conductivity type. Another portion of the gate structure that overlies the adjacent portion of the drift region has a different doping, and overlaps at least a portion of the channel portion, with the threshold voltage associated with the gate structure being influenced by the amount of overlap.

Abstract: An integrated circuit including ESD circuitry that is shared among more than one terminal segment of the integrated circuit to discharge current from an ESD event on any of the terminal segments. The shared ESD circuitry includes a clamp circuit that is coupled to power buses of each segment to discharge current from ESD events on each segment. The shared ESD circuitry includes a trigger circuit that is coupled to nodes coupled to terminals of each segment to detect an ESD event on each segment.

Abstract: A sample-and-hold circuit is provided. The sample-and-hold circuit includes an input one or more dedicated capacitive elements, one or more parasitic capacitive elements connected to said one or more dedicated capacitive elements, an output, a group of switches, and a control unit. The control unit controls said switches so as to interconnect said input, said one or more dedicated capacitive elements, and said output in a cyclic manner in accordance with a sample-and-hold cycle.

Abstract: The embodiments described herein provide antifuse devices and methods that can be utilized in a wide variety of semiconductor devices. In one embodiment a semiconductor device is provided that includes an antifuse, a first diode coupled with the antifuse in a parallel combination, and a second diode coupled in series with the parallel combination. In such an embodiment the first diode effectively provides a bypass current path that can reduce the voltage across the antifuse when other antifuses are being programmed. As such, these embodiments can provide improved ability to tolerate programming voltages without damage or impairment of reliability.

Abstract: A circuit and method for regulating an output voltage are provided. The circuit includes a fully differential first stage amplifier, a second stage amplifier, and a power output driver transistor. The first stage amplifier receives a reference voltage and feedback voltage relative to an output voltage of the power output driver transistor. A differential output of the first stage amplifier is received at differential inputs of the second stage amplifier. The second stage amplifier provides a voltage at a control terminal of the power transistor. The output voltage of the power transistor is based on the voltage at the control terminal and a supply voltage coupled to the power output driver transistor.

Abstract: A mechanism for reducing stiction in a MEMS device by decreasing surface area between two surfaces, such as a travel stop and travel stop region, that can come into close contact is provided. Reduction in contact surface area is achieved by increasing surface roughness of the travel stop region. This is achieved by depositing a polysilicon layer over a dielectric layer using gaseous hydrochloric acid as one of the reactants. A subsequent etch back is performed to further increase the roughness. The deposition of polysilicon and subsequent etch back may be repeated one or more times in order to obtain the desired roughness. A final polysilicon layer may then be deposited to achieve a desired thickness. This final polysilicon layer is patterned to form the travel stop regions. The rougher surface decreases the surface area available for contact and, in turn, decreases the area through which stiction can be imparted.

Abstract: Methods and systems are disclosed for multiple connection management for Bluetooth (BT) devices, and more particularly for BT Low Energy (BLE) devices, to multiple different bonded BT peer devices. A BT device database within a non-volatile memory (NVM) stores identification and persistent information for each bonded BT peer device. At power-on reset (PoR), only device identification information (DII) data, such as an address (ADDR) and an IRK (identity resolving key), for each bonded BT peer device is copied from the NVM to a volatile memory that is used for run-time operation. When a bonded BT peer device forms an active connection, it is identified using the DII data, and its persistent data is copied from NVM to volatile memory as run-time data. The BT device then communicates with the actively connected BT peer device at least in part using the run-time data for the actively connected BT peer device.

Abstract: An integrated antenna package includes an interposer, an integrated circuit die, and a cap that forms a cavity within the integrated antenna package. A lossy EBG structure resides at the cap overlying the integrated circuit device. A lossless EBG structure resides at the cap overlying a microstrip feedline. A radar module includes a plurality of receive portions, each receive portion including a parabolic structure having a reflective surface, an absorber structure, a lens, and an antenna.