Patents Assigned to NXP
  • Patent number: 8966306
    Abstract: A system and method for operating an electronic device having a High-Definition Multimedia Interface port that is shared between an HDMI source function and an HDMI sink function of the electronic device utilizes detecting whether an external HDMI device that is attached to the HDMI port is one of an HDMI source and an HDMI sink. If the external HDMI device is detected as being an HDMI source, the HDMI sink function of the electronic device is enabled. If the external HDMI device is detected as being an HDMI sink, the HDMI source function of the electronic device is enabled.
    Type: Grant
    Filed: May 4, 2011
    Date of Patent: February 24, 2015
    Assignee: NXP, B.V.
    Inventor: Nicolas Guillerm
  • Publication number: 20150052340
    Abstract: Embodiments of a method for operating an event-driven processor and an event-driven processor are described. In one embodiment, a method for operating an event-driven processor involves configuring a heartbeat timer of the event-driven processor and handling an event using the event-driven processor based on the heartbeat timer. Using a heartbeat timer built into the event-driven processor, the task execution determinism of the event-driven processor is improved and the power consumption of the event-driven processor is reduced. Other embodiments are also described.
    Type: Application
    Filed: August 15, 2013
    Publication date: February 19, 2015
    Applicant: NXP B.V.
    Inventors: Adam Fuks, Sergio Scaglia
  • Publication number: 20150049403
    Abstract: Embodiments of an electrostatic discharge (ESD) protection device and a method of operating an ESD protection device are described. In one embodiment, an ESD protection device for an integrated circuit (IC) device includes a bigFET configured to conduct an ESD current during an ESD event and a trigger device configured to trigger the bigFET during the ESD event. The trigger device includes a slew rate detector configured to detect the ESD event, a driver stage configured to drive the bigFET, and a keep-on latch configured to keep the driver stage turned on to drive a gate terminal of the bigFET with a driving voltage that is insensitive to a pre-bias on a drain terminal or a source terminal of the bigFET. Other embodiments are also described.
    Type: Application
    Filed: August 15, 2013
    Publication date: February 19, 2015
    Applicant: NXP B.V.
    Inventors: Gijs de Raad, Paul Cappon, Albert Jan Huitsing
  • Patent number: 8958761
    Abstract: An R.F. transmitter circuit has an amplifier (30), a matching network (40) coupled to an output of the amplifier, a programmable resistance (35) coupled to the output of the amplifier, and a controller (60) arranged to control the programmable resistance, and to determine a matched output impedance of the amplifier by detecting a change in the amplifier output for different values of the programmable resistance. This output impedance can be used to adjust the matching to achieve optimum gain or optimum efficiency or other characteristic, during manufacture, test, or in use.
    Type: Grant
    Filed: October 18, 2007
    Date of Patent: February 17, 2015
    Assignee: NXP, B.V.
    Inventor: Hendrik A. Visser
  • Patent number: 8956920
    Abstract: Embodiments of a method for preparing a leadframe for integrated circuit (IC) die packaging in a molded package with an exposed die pad are disclosed. In one embodiment, a method involves producing a leadframe with a die pad, wherein the die pad has a top surface, a bottom surface, and a perimeter edge. The die pad is then planarized to flatten burrs that may exist at the perimeter edge of the die pad, wherein planarizing the die pad comprises embedding tool markings in the die pad at the perimeter edge of the die pad, the tool markings including a series of peaks and valleys that run parallel to the perimeter edge at all locations around the perimeter edge. Embodiments of a leadframe for IC die packaging in a molded package are also disclosed.
    Type: Grant
    Filed: June 1, 2012
    Date of Patent: February 17, 2015
    Assignee: NXP B.V.
    Inventors: Tsung Yi Wu, Chyi Keh Chern, Tsung Wen Chang
  • Patent number: 8957500
    Abstract: A high-voltage metal capacitor with easy integration into existing semiconductor manufacturing processes can provide isolation capacitors up to several kilovolts. The capacitor includes a support layer with internal structure, including a lower place, a bond pad on the support layer, an upper plate disposed on the support layer, the upper plate being arranged above the lower plate, a dielectric layer, at least part of which is between the lower and upper plates, and a passivation layer, at least part of which covers at least part of the upper plate and part of the dielectric layer. A first opening extends from the surface through the passivation and dielectric layers to the lower plate, and a second opening extends from the surface through the passivation layer to the upper plate. A method of manufacturing the capacitor.
    Type: Grant
    Filed: October 10, 2012
    Date of Patent: February 17, 2015
    Assignee: NXP B.V.
    Inventors: Jerôme Guillaume Anna Dubois, Piet Wessels
  • Patent number: 8959133
    Abstract: A configurable fast Fourier transforms (FFT) apparatus to compute radix-2 and non-radix-2 calculations. The configurable FFT apparatus includes a data input, a data output, an interconnect, and a configuration manager. The data input retrieves an input data segment from a memory device. The data output stores processed data to the memory device. The interconnect routes radix FFT signals of multi-type radix configurations from the data input to the data output. The configuration manager dynamically configures the interconnect according to a determination of a current radix configuration.
    Type: Grant
    Filed: April 14, 2009
    Date of Patent: February 17, 2015
    Assignee: NXP, B.V.
    Inventors: Yanmeng Sun, Liangliang Hu
  • Patent number: 8958248
    Abstract: Flash memory arrays are described. In one embodiment, a flash memory array includes memory sectors of Two-Transistor (2T) AND memory cells. Within each of the memory sectors, a row of sector selection transistors is configured such that writing data onto a memory column within the memory sector is controlled by applying a voltage to a bit line, independent from the row of sector selection transistors. Other embodiments are also described.
    Type: Grant
    Filed: March 14, 2013
    Date of Patent: February 17, 2015
    Assignee: NXP B.V.
    Inventors: Michiel Jos van Duuren, Maurits Mario Nicolaas Storms, Erik Maria van Bussel
  • Patent number: 8957859
    Abstract: An apparatus for misalignment compensation in optical joysticks is described. The optical joystick includes a light source, a plurality of photodetectors, and circuitry for controlling operation of the optical joystick. In some embodiments, each of the photodetectors may partitioned into a plurality of photodetector elements and select photodetector elements are configured to be individually activated in order to cause an electrical shifting of the selected photodetector elements to achieve a different operational alignment position of optical components of the optical joystick. In some embodiments, the light source may be similarly be calibrated by individually activating portions of a light-source array to cause an electrical shift. Various other embodiments and methods of operation are also described.
    Type: Grant
    Filed: April 12, 2011
    Date of Patent: February 17, 2015
    Assignee: NXP, B.V.
    Inventors: Kim Phan Le, Sebastien Mouy
  • Patent number: 8958563
    Abstract: A method for generating a public key for an electronic device is provided, wherein the method comprises generating a public key 103 based on a private key and a unique identifier associated with the electronic device 200.
    Type: Grant
    Filed: April 28, 2008
    Date of Patent: February 17, 2015
    Assignee: NXP B.V.
    Inventors: Heike Neumann, Paul Hubmer
  • Patent number: 8957687
    Abstract: The invention relates to an electrochemical sensor integrated on a substrate, the electrochemical sensor including: a field effect transistor integrated on the substrate and having a source, gate and drain connections, said gate of the field effect transistor including: a sensing gate conductively coupled to a sensing electrode; and a bias gate, wherein the sensing gate is capacitively coupled to the bias gate and the bias gate is capacitively coupled to the substrate.
    Type: Grant
    Filed: April 26, 2012
    Date of Patent: February 17, 2015
    Assignee: NXP, B.V.
    Inventors: Axel Nackaerts, Matthias Merz, Youri Victorovitch Ponomarev
  • Publication number: 20150041862
    Abstract: Disclosed is a method of manufacturing an integrated circuit comprising a bipolar transistor, the method comprising providing a substrate (10) comprising a pair of first isolation regions (12) separated from each other by an active region (11) comprising a collector impurity said bipolar transistor; forming a base layer stack (14, 14?) over said substrate; forming a further stack of a migration layer (15) having a first migration temperature and an etch stop layer (20) over said base layer stack (14); forming a base contact layer (16) having a second migration temperature over the further stack, the second migration temperature being higher than the first migration temperature; etching an emitter window (28) in the base contact layer over the active region, said etching step terminating at the etch stop layer; at least partially removing the etch stop layer, thereby forming cavities (29) extending from the emitter window in between the base contact layer and the redistribution layer; and exposing the resultan
    Type: Application
    Filed: October 27, 2014
    Publication date: February 12, 2015
    Applicant: NXP B.V.
    Inventors: Johannes Josephus Theodorus Marinus DONKERS, Petrus Hubertus Cornelis MAGNEE, Blandine DURIEZ, Evelyne GRIDELET, Hans MERTENS, Tony VANHOUCKE
  • Patent number: 8954767
    Abstract: Consistent with an example embodiment, there is a power regulator arrangement with variable current capacity providing power from a power supply to a load having variable demand. As a load, a high-performance microprocessor has several modes of operation. At the highest speed setting, it demands a lot of current. At slower clock speeds and during state retention, the processor has a very low current consumption. Using a single regulator, the current efficiency may be very low during long standby periods. To increase the efficiency even at lower load currents, a scheme is based on parallel operation of multiple regulators having different load ranges, for example, a “low, “medium,” and “high” range regulators. Having knowledge of the load current profile, the regulators can be adjusted such that the peak of the efficiency curve matches the load profile of the regulator. The efficiency of the power regulator arrangement is enhanced throughout the range of power demanded by the load.
    Type: Grant
    Filed: May 6, 2013
    Date of Patent: February 10, 2015
    Assignee: NXP B.V.
    Inventors: Andre Gunther, Kevin Mahooti, Meng Hao
  • Patent number: 8952976
    Abstract: A SIMD parallel processor is described comprising an array comprising processing elements, associated data storage components and access means configured to enable access to at least one of the data storage components associated with at least one of the processing elements; a control processor; memory control means configured to enable addressing of at least one of the access means for the control processor; and connecting means configured to connect the memory control means to the access means.
    Type: Grant
    Filed: August 5, 2009
    Date of Patent: February 10, 2015
    Assignee: NXP B.V.
    Inventors: Alexander Alexandrovich Danilin, Richard Petrus Kleihorst, Paul Wielage
  • Patent number: 8954778
    Abstract: An electronic timekeeping circuit and a method for operating an electronic timekeeping circuit are described. In one embodiment, an electronic timekeeping circuit includes power supplies and timekeeping circuit components that are grouped into power supply domains. Power is supplied to each of the power supply domains by a corresponding one of the power supplies. Timekeeping registers are duplicated for each of the power supply domains. The timekeeping registers are synchronized between the power supply domains if one of the timekeeping registers is modified or if one of the power supplies is turned off and subsequently turned back on. Other embodiments are also described.
    Type: Grant
    Filed: June 30, 2011
    Date of Patent: February 10, 2015
    Assignee: NXP B.V.
    Inventors: Peter Robertson, Allen Mann
  • Patent number: 8946042
    Abstract: Disclosed is a method of manufacturing a bipolar transistor, comprising providing a substrate (10) comprising a first isolation region (12) separated from a second isolation region by an active region (11) comprising a collector impurity; forming a layer stack over said substrate, said layer stack comprising a base layer (14, 14?), a silicon capping layer (15) over said base layer and a silicon-germanium (SiGe) base contact layer (40) over said silicon capping layer; etching the SiGe base contact layer to form an emitter window (50) over the collector impurity, wherein the silicon emitter cap layer is used as etch stop layer; forming sidewall spacers (22) in the emitter window; and filling the emitter window with an emitter material (24). A bipolar transistor manufactured in accordance with this method and an IC comprising one or more of such bipolar transistors are also disclosed.
    Type: Grant
    Filed: February 11, 2014
    Date of Patent: February 3, 2015
    Assignee: NXP, B.V.
    Inventors: Evelyne Gridelet, Johannes Josephus Theodorus Marinus Donkers, Tony Vanhoucke, Petrus Hubertus Cornelis Magnee, Hans Mertens, Blandine Duriez
  • Patent number: 8947149
    Abstract: Embodiments of a clock distribution device and a method of clock distribution are described. In one embodiment, a clock distribution device includes a stacked clock driver circuit configured to perform clock signal charge recycling on input clock signals that swing between different voltage ranges and a load circuit. The stacked clock driver circuit includes stacked driver circuits configured to generate output clock signals that swing between the different voltage ranges. The load circuit includes load networks of different semiconductor types. Each of the load networks are configured to be driven by one of the output clock signals. Other embodiments are also described.
    Type: Grant
    Filed: December 20, 2013
    Date of Patent: February 3, 2015
    Assignee: NXP B.V.
    Inventors: Ajay Kapoor, Ralf Malzahn, Rinze Ida Mechtildis Peter Meijer, Peter Thueringer
  • Patent number: 8949937
    Abstract: A method of accessing in a mobile communication device (4) an application (5, 14, 26), the application (5, 14, 26) being issued by a Service Provider (2), from a trusted application, also known as wallet (12), in which mobile device (4) a secure element (7) such as a SmartMX device is comprised that comprises a service manager (8) that manages the application (5, 14, 26), comprising managing by the service manager (8) a link between the application (5, 14, 26) and an application-codec (6, 15) also being issued by the Service Provider (2), wherein the application-codec (6, 15) is designed for interfacing between the service manager (8) and the application (5, 14, 26) and for processing an access request requesting access to the application (5, 14, 26)received from the service manager (8) and triggered by the wallet (12), and, triggered by the wallet (12), accessing the application (5, 14, 26) via the service manager (8) by means of utilization of the link between the application (5, 14, 26) and the application
    Type: Grant
    Filed: May 19, 2009
    Date of Patent: February 3, 2015
    Assignee: NXP, B.V.
    Inventors: Alexandre Corda, Dominique Brule, Mathew Smith
  • Patent number: 8942381
    Abstract: A method of controlling a loudspeaker output comprises deriving an admittance function over time from the voice coil voltage and current. In combination with a delta function, the force factor of the loudspeaker and the blocked electrical impedance, the input-voltage-to-excursion transfer function over time is obtained. This is used to control audio processing for the loudspeaker thereby to implement loudspeaker protection and/or acoustic signal processing; The invention provides a modelling and control approach which is not based on a parametric model. As a consequence, it does not require prior knowledge regarding the enclosure (e.g. closed or vented box) and can cope with complex designs of the enclosure.
    Type: Grant
    Filed: June 7, 2012
    Date of Patent: January 27, 2015
    Assignee: NXP B.V.
    Inventor: Temujin Gautama
  • Patent number: 8936947
    Abstract: A method of performing a measurement with a sensor having a sensing surface and at least one capture molecule attached to the sensing surface for forming a binding pair with an analyte of interest, the binding pair having a flexible spatial orientation, the method comprising capturing the analyte of interest with the capture molecule, thereby forming the binding pair in an initial spatial orientation; applying a first electromagnetic force to the sensing surface to alter the spatial orientation of the binding pair; and performing a sensor measurement with the binding pair in the altered spatial orientation. A sensor apparatus implementing this method is also disclosed.
    Type: Grant
    Filed: February 18, 2011
    Date of Patent: January 20, 2015
    Assignee: NXP, B.V.
    Inventor: Friso Jacobus Jedema