Patents Assigned to NXP
  • Patent number: 8878444
    Abstract: A controller for a dimmable LED lighting circuit is disclosed, the controller comprising: an LED current controller configured to set a current of a constant current source in dependence on a conduction angle of the phase-cut dimmer; a first feedback circuit configured to control the circuit's power converter in dependence on the constant current source by adjusting an output of the power converter; and a second feedback circuit configured to control a supplementary output load arranged in parallel with the series arrangement of the constant current source and plurality of LEDs, wherein the second feedback circuit is operable to adjust the supplementary output load faster than the first feedback circuit adjusts the output of the power convertor. A driver and lighting circuit also disclosed, as is a method for controlling a dimmable lighting circuit.
    Type: Grant
    Filed: January 22, 2014
    Date of Patent: November 4, 2014
    Assignee: NXP B.V.
    Inventor: Nguyen Trieu Luan Le
  • Publication number: 20140320204
    Abstract: A variety of circuits, methods and devices are implemented for providing an adjustable resistance. According to one such implementation an adjustable resistive device includes a metal-oxide semiconductor (MOS) transistor having a gate, a drain, a source, and a body. First circuitry controls a resistance from drain to source by applying a gate voltage that is a function of a variable control input. Second circuitry adjusts a voltage at the body according to a drain voltage and a source voltage, whereby the resistance from drain to source is substantially linear for a given value of the variable control input and over a voltage range.
    Type: Application
    Filed: December 28, 2009
    Publication date: October 30, 2014
    Applicant: NXP B.V.
    Inventor: Cord-Heinrich Kohsiek
  • Publication number: 20140323350
    Abstract: A lateral test flow arrangement for a test molecule is disclosed, comprising: a test strip for transporting an analyte away from a sampling region and towards an absorbing region, the test strip having therein and remote from the sampling region, a test region for functionalization with a molecule which binds to the test molecule or to a conjugate of the test molecule; a sensing test capacitor having electrodes extending across the test strip at least partially aligned with the test region and being physically isolated therefrom; a reference test capacitor having electrodes extending across the test strip and being physically isolated therefrom; and an electronic circuit configured to measure a time-dependant capacitance difference between the sensing test capacitor and the reference test capacitor.
    Type: Application
    Filed: December 6, 2012
    Publication date: October 30, 2014
    Applicant: NXP B.V.
    Inventors: Viet Nguyen, Franciscus Petrus Widdershoven, Roel Daamen
  • Publication number: 20140320096
    Abstract: The disclosure relates to a voltage generator for providing an output voltage in accordance with a received target signal, the voltage generator comprising: a resonant converter configured to receive an input voltage, the resonant converter comprising: a first switch; a second switch connected in series with the first switch between the input voltage and ground (GND); a resonant tank associated with the second switch; an output capacitor coupled to the resonant tank and configured to provide an output voltage; and a rectifier configured to allow charge to flow in a single direction between the resonant tank and the output capacitor; and a controller configured to receive the target signal and to set an operating parameter of the resonant converter in accordance with a difference between an output value which is related to the output voltage and the target signal.
    Type: Application
    Filed: April 15, 2014
    Publication date: October 30, 2014
    Applicant: NXP B.V.
    Inventor: Frans Pansier
  • Publication number: 20140318854
    Abstract: The invention provides an air cavity package for a component. The package has a connection lead structure in which the or each connection lead has a connection zone within the package for receiving a wire connector. A region of no connection lead material is provided directly between the connection zone and the neighbouring outer edge of the cavity. This provides a trap for flowing interconnect material.
    Type: Application
    Filed: April 21, 2014
    Publication date: October 30, 2014
    Applicant: NXP B.V.
    Inventors: Michael Asis, Albertus Reijs, Tennyson Nguty, An Xiao
  • Publication number: 20140320197
    Abstract: In High Voltage CMOS technologies the supply voltage is typically higher than the maximum allowed gate voltage. In a switching output stage of amplifiers such class-D amplifiers and DC-DC converters the gates of the power field effect transistors need to be charged quickly. This requires a gate driver that is capable of delivering large currents without exceeding the maximum allowed voltage on the gate of the power field effect transistors.
    Type: Application
    Filed: April 21, 2014
    Publication date: October 30, 2014
    Applicant: NXP B.V.
    Inventors: Marco Berkhout, Paulus Petrus Franciscus Maria Bruin
  • Patent number: 8874394
    Abstract: Apparatus and method for IR-drop and supply noise measurements in electronic circuits. A first voltage at a point of interest in the circuit is sampled and stored during a quiescent mode of the circuit the voltage is to be measured in. Subsequently, the circuit is brought in an operating mode and a second voltage is sampled and held at the same point of interest. The first and the second voltage are compared and a corresponding voltage signal is passed to a system output.
    Type: Grant
    Filed: November 18, 2009
    Date of Patent: October 28, 2014
    Assignee: NXP, B.V.
    Inventors: Hendricus Joseph Maria Veendrick, Marcel Pelgrom, Victor Zieren
  • Patent number: 8874858
    Abstract: A reconfigurable interleaver is provided, configured to produce a sequence of interleaved addresses, configurable for at least two different interleaving patterns. The reconfigurable interleaver comprises a plurality of reconfigurable counters. The number of values that the counters count is configurable as are their start values. The interleaver further comprises a plurality of memory in which the counters indicate memory positions so that values may be retrieved. Computational elements compute an interleaved sequence of addresses in dependency on the retrieved values. By reconfiguring the counters and possibly changing the content of the memories, the interleaver may be configured for a different interleaving pattern.
    Type: Grant
    Filed: June 9, 2011
    Date of Patent: October 28, 2014
    Assignee: NXP, B.V.
    Inventor: Nur Engin
  • Patent number: 8872761
    Abstract: The invention relates to a pointing device and a method for processing signals from such a pointing device, said device comprising a base and an actuator movable with respect to the base, and a detector, said detector adapted for providing at least first and second positional signals indicating a position of the actuator with respect to the base along corresponding first and second axes, wherein said signal processing method comprises the steps of converting the at least two positional signals into a polar coordinate signal comprising a magnitude signal, and thresholding the magnitude signal of the polar coordinate signal to provide a thresholded magnitude signal. In an embodiment the method further comprising the step of applying a conversion curve to the thresholded magnitude signal to produce a velocity magnitude signal.
    Type: Grant
    Filed: August 11, 2009
    Date of Patent: October 28, 2014
    Assignee: NXP, B.V.
    Inventor: Kim Le Phan
  • Patent number: 8872290
    Abstract: A sensor is provided for sensing a value of a physical parameter characteristic of the sensor's environment. The sensor is implemented in semiconductor technology. A behavior of the sensor's electronic circuitry is affected by stress. The stress is induced by a film covering the circuitry or only part thereof. The stress is caused by the film's material, whose dimensions depend on a value of the parameter. This dependence is different from the 5 dependence of the circuitry's substrate on the same parameter.
    Type: Grant
    Filed: July 30, 2009
    Date of Patent: October 28, 2014
    Assignee: NXP B.V.
    Inventors: Romano Hoofman, Remco Henricus Wilhelmus Pijnenbrug, Youri Victorovitch Ponomarev
  • Patent number: 8872596
    Abstract: The present invention relates to a polar signal generator and method of deriving phase and amplitude components from in-phase (I) and quadrature-phase (Q) components of an input signal, wherein the I and Q components are generated at a first sampling frequency based on the input signal, and are then up-sampled in accordance with a predetermined first interpolation factor (N), to generate up-sampled I and Q components at a second sampling frequency higher than the first sampling frequency. The up-sampled I and Q components are converted into the phase and amplitude components, wherein the converting step is operated at the second sampling frequency. Moreover, the phase and amplitude components can be further up-sampled, optionally by different sampling frequencies, to a third and a fourth sampling frequency. Thereby, I-Q generation and cartesian-to-polar transformation can be performed at lower frequencies, which reduces power consumption.
    Type: Grant
    Filed: June 6, 2007
    Date of Patent: October 28, 2014
    Assignee: NXP, B.V.
    Inventors: Manel Collados Asensio, Nenad Pavlovic, Vojkan Vidojkovic, Paulus T. M. Van Zeijl
  • Patent number: 8871599
    Abstract: Disclosed is an integrated circuit and a method of manufacturing an integrated circuit comprising a bipolar transistor, the method comprising providing a substrate comprising a pair of isolation regions separated by an active region comprising a collector; forming a base layer stack over said substrate; forming a migration layer having a first migration temperature and an etch stop layer; forming a base contact layer having a second migration temperature; etching an emitter window in the base contact layer, thereby forming cavities extending from the emitter window; and exposing the resultant structure to the first migration temperature in a hydrogen atmosphere, thereby filling the cavities with the migration layer material.
    Type: Grant
    Filed: August 30, 2012
    Date of Patent: October 28, 2014
    Assignee: NXP, B.V.
    Inventors: Johannes Josephus Theodorus Marinus Donkers, Petrus Hubertus Cornelis Magnee, Blandine Duriez, Evelyne Gridelet, Hans Mertens, Tony Vanhoucke
  • Patent number: 8872237
    Abstract: Disclosed is a method of manufacturing a heterojunction bipolar transistor comprising a substrate, an upper region of said substrate comprising an active region of the bipolar transistor bordered by shallow trench insulation, said active region comprising a buried collector region extending to a depth beyond the depth of the shallow trench insulation, the method comprising forming a trench in the substrate adjacent to said active region, said trench extending through the shallow trench insulation; at least partially filling said trench with an impurity; and forming a collector sinker in the substrate by developing said impurity to extend into the substrate to a depth beyond the depth of the shallow trench insulation. An IC comprising a heterojunction bipolar transistor manufactured by this method is also disclosed.
    Type: Grant
    Filed: November 18, 2011
    Date of Patent: October 28, 2014
    Assignee: NXP, B.V.
    Inventors: Tony Vanhoucke, Johannes Josephus Theodorus Marinus Donkers, Hans Mertens, Blandine Duriez, Evelyne Gridelet
  • Patent number: 8872359
    Abstract: A method of manufacturing a MEMS device comprises forming a MEMS device element (12). A sidewall (20) is formed around the MEMS device element, and a sacrificial layer (14) is formed over the device element and within the sidewall. A package cover layer (16) is provided over the sacrificial layer, and the sacrificial layer is removed. This method provides additional sidewalls to the cap provided over the MEMS device. These additional sidewalls can then be deposited by a different process and be formed of a different material to the top part of the package cover layer. The sidewalls can prevent reflow of the sacrificial layer and improve the sealing properties of the sidewalls.
    Type: Grant
    Filed: June 24, 2010
    Date of Patent: October 28, 2014
    Assignee: NXP, B.V.
    Inventors: Bart Van Velzen, Hans Van Zadelhoff, Greja Johanna Adriana Maria Verheijden
  • Patent number: 8872588
    Abstract: An amplifier comprising at least one amplifying element (20a, 25a) and a biasing circuit (32a, 32b) for biasing the or each amplifying element with a bias voltage is disclosed. The biasing circuit (32a, 32b) is adapted to vary the bias voltage such that the or each amplifying element switches between non-switching and switching modes of operation in response to a bias control signal (4) passing through a threshold value.
    Type: Grant
    Filed: March 7, 2012
    Date of Patent: October 28, 2014
    Assignee: NXP, B.V.
    Inventors: Kim Li, Simon Peter Goddard
  • Patent number: 8872520
    Abstract: The present invention relates to a sensor comprising a substrate (10) carrying a field effect transistor (30) having a gate electrode (32), the sensor further comprising a measurement electrode (36) spatially separated from the gate electrode; and a reference electrode (40), said measurement electrode being in configurable conductive contact with said gate electrode, the sensor further comprising a charge storage element (60) comprising a first electrode connected to a node (38) between the measurement electrode and the gate electrode; and a second electrode configurably connected to a known potential source (80). The present invention further relates to a method of performing a measurement with such a sensor.
    Type: Grant
    Filed: January 20, 2011
    Date of Patent: October 28, 2014
    Assignee: NXP, B.V.
    Inventors: Axel Nackaerts, Matthias Merz
  • Publication number: 20140312356
    Abstract: A semiconductor device and a method of making the same. The device includes a semiconductor substrate. The device also includes a bipolar transistor on the semiconductor substrate. The bipolar transistor includes an emitter. The bipolar transistor also includes a base located above the emitter. The bipolar transistor further includes a laterally extending collector located above the base. The collector includes a portion that extends past an edge of the base.
    Type: Application
    Filed: March 24, 2014
    Publication date: October 23, 2014
    Applicant: NXP B.V.
    Inventors: Tony Vanhoucke, Viet Thanh Dinh, Anco Heringa, Dirk Claasen, Evelyne Gridelet, Jan Willem Slotboom
  • Publication number: 20140312787
    Abstract: Controllers (360, 360?), lighting circuits and methods are disclosed, for a dimmable LED lighting circuit having a series arrangement of two types of LED, the controller comprising a control circuit (330), a bypass circuit (340) and optionally a further bypass circuit and being operable for controlling a current, the current (Idriver) being separable into first and second parts (IW, IB), and into further first and second parts, wherein the controller is configured to direct the (further) first part through the LED or LEDs of the second (first) type and direct the (further) second part through the (further) bypass circuit (respectively), and wherein the control circuit is configured to adjust the ratio between the first, or further first, part and the second, or further second respectively, part in dependence on a dimming level of the LED lighting circuit.
    Type: Application
    Filed: April 15, 2014
    Publication date: October 23, 2014
    Applicant: NXP B.V.
    Inventor: Leendert VAN DEN BROEKE
  • Publication number: 20140315485
    Abstract: A device includes a near field communication (NFC) circuit (114) that is configured and arranged to communicate data with external devices (102). An internal communication circuit (112) communicates data over a microprocessor bus (110). A secure memory circuit (118) stores an identifier that is unalterable in the secure memory circuit. Logic circuitry (116) performs a secure transaction protocol.
    Type: Application
    Filed: April 19, 2013
    Publication date: October 23, 2014
    Applicant: NXP B.V.
    Inventor: Julien Marie
  • Publication number: 20140317433
    Abstract: This invention provides a clock control circuit, which can be added to any pipeline-processor to solve timing problems arising from variations due to process outcome and environmental conditions. Critical instructions are detected (instructions that exercise critical paths) in conjunction with environmental sensing (such as process, temperature and voltage). This information is used to control cycle stealing.
    Type: Application
    Filed: April 3, 2014
    Publication date: October 23, 2014
    Applicant: NXP B.V.
    Inventors: Hamed FATEMI, Rinze Ida Mechtildis Peter MEIJER, Ghiath AL-KADI, Surendra GUNTUR, Jan HOOGERBRUGGE