Patents Assigned to NXP
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Patent number: 8364832Abstract: A wireless communication device comprises an input terminal configured to communicate data with a processor. A segregation circuit (150) is coupled to the input terminal and configured to identify predetermined data and to separate more important data from less important data. A memory (112) is configured to store at least one parameter relevant to the wireless communication protocol. A modem (110) is coupled to segregation circuit and the memory (112) and is configured to communicate using a wireless protocol over a wireless channel, and includes a framer (152) configured to fragment the segregated data based at least in part on the at least one parameter stored in the memory. In one aspect of the invention, the wireless protocol is 802.11. Advantages of the invention include the ability to achieve high quality video communication over a wireless communication link with less chance of dropping important data.Type: GrantFiled: August 26, 2004Date of Patent: January 29, 2013Assignee: NXP B.V.Inventor: Pen Li
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Patent number: 8362821Abstract: An electronic device comprising a generator for generating a stream of charge carriers. The generator comprises a bipolar transistor having an emitter region, a collector region and a base region oriented between the emitter region and the collector region, and a controller for controlling exposure of the bipolar transistor to a voltage in excess of its open base breakdown voltage (BVCEO) such that the emitter region generates the stream of charge carriers from a first area being smaller than the emitter region surface area. The electronic device may further comprise a material arranged to receive the stream of charge carriers for triggering a change in a property of said material, the emitter region being arranged between the base region and the material.Type: GrantFiled: November 12, 2008Date of Patent: January 29, 2013Assignee: NXP B.V.Inventors: Tony Vanhoucke, Godefridus A. M. Hurkx, Jan W. Slotboom
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Patent number: 8363115Abstract: The invention concerns a method for digital image stabilization for removing jitter from an original sequence of images (10) generated by a camera. The original sequence (10) is applied to a stabilization algorithm (11). The global motion of a camera is estimated and filtered (110) using a default motion filter. Predetermined parameters (13, 140, 141) are extracted from both the original (10) and stabilized (12) sequences of images. A measure value is computed in order to evaluate (15) the stabilization quality and compared to a threshold. Depending on the results of the evaluation (O15, O?15) the stabilization algorithm (11) uses an alternative filter, in order to improve stabilization quality, or continues to use the default filter.Type: GrantFiled: August 9, 2006Date of Patent: January 29, 2013Assignee: NXP, B.V.Inventors: Stephane Auberger, Carolina Miro, Yann Picard
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Patent number: 8362765Abstract: The invention relates to a method and a sensor device (1) for measuring a magnetic field comprising a first circuit (4) including a magneto sensitive sensor element (2) and a current source (5) and a second circuit (6) including a signal generator (7) and a coil (3) producing a excitational magnetic field at the sensor element (2), wherein the output signal of the sensor element is processible such that a second derivative of the sensor signal and the signal of the signal generator are derivable which are processible such that a countable signal is resulting being a measure of the magnetic field.Type: GrantFiled: August 27, 2008Date of Patent: January 29, 2013Assignee: NXP B.V.Inventors: Stefan Butzmann, Marcus Prochaska
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Publication number: 20130021145Abstract: Object tracking is facilitated. In accordance with one or more embodiments, an object tracking apparatus (200) includes a proximate-range circuit (212), a positioning circuit (214) and a communications circuit (216). The proximate-range circuit wirelessly verifies the identity and presence of at least one proximate-range communications device (220), and the positioning circuit determines positioning information of the object tracking apparatus. The communications circuit receives outputs from the proximate-range circuit and positioning circuit respectively regarding the verification and positioning information, and wirelessly communicates data to a remote communications station based upon the received outputs (140).Type: ApplicationFiled: July 2, 2012Publication date: January 24, 2013Applicant: NXP B.V.Inventor: Cedric Boudy
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Patent number: 8358370Abstract: The invention refers to a flash light compensation system and corresponding method for digital camera systems, wherein a luminance compensation is carried out on an image of a scene (3) picked-up by an image sensor (1), on the basis of a respective intensity field measured by a plurality of sensors (4, 5), when the scene is illuminated by flash light emitted by a flash device (2). Depending upon the output signals of the plurality of sensors a depth field of the scene is estimated, and this estimation provides a basis for the luminance adjustment on the scene picked up as an image while illuminated by the flash device. The system and method is suitable for effectively reducing the problem of unevenly distributed lighting on a picked-up image of the scene.Type: GrantFiled: December 3, 2008Date of Patent: January 22, 2013Assignee: NXP B.V.Inventors: Richard Petrus Kleihorst, Serafim Efstratiadis
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Patent number: 8357971Abstract: A Trench gate MOS field-effect transistor having a narrow, lightly doped, region extending from a channel accommodating region (3) of same conductivity type immediately adjacent the trench sidewall. The narrow region may be self-aligned to the top of a lower polysilicon shield region in the trench or may extend the complete depth of the trench. The narrow region advantageously relaxes the manufacturing tolerances, which otherwise require close alignment of the upper polysilicon trench gate to the body-drain junction.Type: GrantFiled: October 22, 2008Date of Patent: January 22, 2013Assignee: NXP B.V.Inventors: Steven Thomas Peake, Philip Rutter, Christopher Martin Rogers, Miron Drobnis, Andrew Butler
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Patent number: 8357979Abstract: An electronic device comprising a field-effect transistor having an inter digitated structure suitable for high-frequency power applications, and having multiple threshold voltages that are provided in different regions of each a segment of the interdigitated structure. This leads to a dramatic improvement in linearity over a large power range in the back-off region under class AB signal operation.Type: GrantFiled: April 28, 2004Date of Patent: January 22, 2013Assignee: NXP B.V.Inventors: Thomas Christian Roedle, Hendrikus Ferdinand Franciscus Jos, Stephan Jo Cecile Henri Theeuwen, Petra Christina Anna Hammes, Radjindrepersad Gajadharsing
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Patent number: 8357920Abstract: An electronic component (100) comprising a matrix (102) and a plurality of islands (103) embedded in the matrix (102) and comprising a material which is convertible between at least two states characterized by different electrical properties, wherein the plurality of islands (103) form a continuous path (104) in the matrix (102).Type: GrantFiled: April 17, 2008Date of Patent: January 22, 2013Assignee: NXP B.V.Inventor: Friso Jacobus Jedema
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Patent number: 8358175Abstract: An oscillator architecture and a method for powering up/down the oscillator architecture are described. In one embodiment, an oscillator architecture includes a reference generator configured to generate reference signals and an in-phase/quadrature (IQ) oscillator configured to generate oscillation signals based on the reference signals. The reference generator includes a distributed start-up circuitry that includes multiple start-up circuits. The IQ oscillator includes at least one turbo comparator having a low power functional mode and a turbo functional mode. Other embodiments are also described.Type: GrantFiled: May 10, 2011Date of Patent: January 22, 2013Assignee: NXP B.V.Inventors: Kevin Mahooti, Sanket Gandhi, Min Ming Tarng
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Publication number: 20130016791Abstract: A method and apparatus for receiving a media stream provided in a plurality of different, alternative encoded representations. Each representation comprises a series of discrete fragments and each fragment comprises a contiguous temporal segment of the stream. The method comprises: obtaining (240, 310) at least a part of a first fragment from a first one of the representations; obtaining (210, 320) at least a part of a second fragment from a second one of the representations, wherein the first and second fragments comprise temporal segments that overlap at least partially; decoding (250, 330) a first temporal segment of the media stream from the first fragment; and decoding (260, 350) a second, later temporal segment of the media stream from the second fragment. In this way, the method switches from receiving the stream in the first representation to receiving it in the second representation.Type: ApplicationFiled: July 3, 2012Publication date: January 17, 2013Applicant: NXP B.V.Inventors: Arnaud Collard, Nicolas Delahaye
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Publication number: 20130016533Abstract: Consistent with an example embodiment there is a method of controlling a resonant power converter; the power converter includes first and second series connected switches connected between a supply voltage line and a ground line and a resonance circuit, having a capacitor and an inductor. The resonance circuit is connected to a node connecting the first and second switches. The method comprises repeated sequential steps of closing the first switch to start a conduction interval; sampling a voltage across the capacitor to obtain a sampled voltage level; and opening the first switch to end the conduction interval when a voltage across the capacitor crosses a voltage level determined by addition of the sampled voltage level with a predetermined voltage difference; wherein controlling the predetermined voltage difference determines a power output of the resonant power converter.Type: ApplicationFiled: July 11, 2012Publication date: January 17, 2013Applicant: NXP B.V.Inventor: Hans Halberstadt
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Patent number: 8354886Abstract: A signal processing arrangement comprises an amplifier (AMP V1) that includes a stage with complementary transistors (MP3, MN3) of opposite conductivity type arranged in series between two supply lines (+, ?). A controllable biasing circuit (CCS) is provided for changing a quiescent operating point of the stage as a function of a control signal (CS). A control arrangement measures an even order 5 distortion of the amplifier (AMP V1) and adjusts the control signal (CS) so that the even order distortion is below a critical level.Type: GrantFiled: August 10, 2009Date of Patent: January 15, 2013Assignee: NXP B.V.Inventor: Johannes Hubertus Antonius Brekelmans
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Publication number: 20130013261Abstract: Metering system (200) comprising a metrology unit (120) configured for obtaining digital metrology data representing a measured physical quantity representing use of a utility (210), a controller (110) configured for transmitting protected usage information based on the digital metrology data to an external server (220), and a secure element (240), wherein the secure element is arranged between the metrology unit and the controller, the secure element being connected to the metrology unit for receiving from the metrology unit the digital metrology data, the secure element being connected to the controller for sending the protected usage information to the controller, and the secure element comprises a local storage (246) for storing data dependent upon the received digital metrology data, the stored data representing the received digital metrology data for at least a predetermined period of time.Type: ApplicationFiled: July 3, 2012Publication date: January 10, 2013Applicant: NXP B.V.Inventors: Patrick Niessen, Jan Rene Brands
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Publication number: 20130009716Abstract: A MEMS resonator has a resonator mass in the form of a closed ring anchored at points around the ring. A set of ring comb electrode arrangements is fixed to the ring at locations between the anchor points, to couple the input (drive) and output (sense) signals to/from the resonator mass.Type: ApplicationFiled: June 29, 2012Publication date: January 10, 2013Applicant: NXP B.V.Inventor: Kim PHAN LE
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Patent number: 8350308Abstract: A read only memory is manufactured with a plurality of transistors (4) on a semiconductor substrate (2). A low-k dielectric (10) and interconnects (14) are provided over the transistors (4). To program the read only memory, the low-k dielectric is implanted with ions (22) in unmasked regions (20) leaving the dielectric unimplanted in masked regions (18). The memory thus formed is difficult to reverse engineer.Type: GrantFiled: March 5, 2009Date of Patent: January 8, 2013Assignee: NXP B.V.Inventors: Aurelie Humbert, Pierre Goarin, Romain Delhougne
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Patent number: 8349726Abstract: There is described a method of fabricating a dual damascene structure for a semiconductor device. A halogen based pre-cursor is used during vapor deposition of a diffusion barrier layer in a trench or via formed in a substrate. Residual halogen from the deposition is allowed to remain on the barrier layer and is used to catalyse growth of a metal layer on the barrier layer to fill the trench or via.Type: GrantFiled: September 15, 2006Date of Patent: January 8, 2013Assignee: NXP B.V.Inventor: Wim Besling
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Patent number: 8350597Abstract: The present invention relates to a low-voltage self-calibrated peak detector (100). Using a two-step calibration process that compensates the offset errors introduced by the respective first, second and third comparators (122, 128, 130), the peak detection is made accurate whatever temperature, process or mismatch spreads. Its input bandwidth can be as high as the bandwidth of an operational amplifier of unity gain. In a rail-to-rail configuration, it can be implemented into a fully differential low-voltage self-calibrated CMOS peak detector (200), which can have a very high conversion gain (?) and a very high input signal dynamic ranging.Type: GrantFiled: October 7, 2009Date of Patent: January 8, 2013Assignee: NXP B.V.Inventor: Jean-Robert Tourret
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Patent number: 8351232Abstract: Various exemplary embodiments relate to a power factor corrector for low loads and a related method. The power factor corrector raises power factor at low loads or high mains voltages by having the a greater amount of current delivered to the load during the falling time of the absolute value of the mains AC voltage than during the applicable rising time. Various embodiments achieve this by increasing the switch-on time of a control switch during the falling time so that the majority of the switch-on time during a mains period occurs during the falling time. This may involve using a timing voltage increasing over a period within each half mains cycle to increase the switch-on time of conversion cycles in the falling time. This may also involve shifting the power conversion in time domain during each half mains cycle so that a majority of the time occurs during the falling time. Various embodiments may employ both methods.Type: GrantFiled: December 28, 2009Date of Patent: January 8, 2013Assignee: NXP B.V.Inventor: Cheng Zhang
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Patent number: 8350385Abstract: The present invention relates to a stress buffering package (49) for a semiconductor component, with a semiconductor substrate (52); an I/O pad (54), electrically connected to the semiconductor substrate (52); a stress buffering element (74) for absorbing stresses, electrically connected to the I/O pad (54); an underbump metallization (70), electrically connected to the stress buffering element (74); a solder ball (60), electrically connected to the underbump metallization (70); a metal element (61) between the solder ball (60) and the semiconductor substrate (52); a passivation layer (56, 58), which protects the semiconductor substrate (52) and the metal element (61) and which at least partially exposes the I/O pad (54); characterized in that a roughness of an interface between the stress buffering element (74) and the passivation layer (56, 58) is lower than a roughness of an interface between the metal element (61) and the passivation layer (56, 58).Type: GrantFiled: July 15, 2008Date of Patent: January 8, 2013Assignee: NXP B.V.Inventor: Hendrik Hochstenbach