Patents Assigned to NXP
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Publication number: 20120262242Abstract: A resonator in which in addition to the normal anchor at a nodal point, a second anchor arrangement is provided and an associated connecting arm between the resonator body and the second anchor arrangement. The connecting arm connects to the resonator body at a non-nodal point so that it is not connected to a normal position where fixed connections are made. The connecting arm is used to suppress transverse modes of vibration.Type: ApplicationFiled: April 13, 2012Publication date: October 18, 2012Applicant: NXP B.V.Inventors: Casper van der Avoort, Jozef Thomas Martinus Van Beek
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Publication number: 20120260732Abstract: A sensor (2) for sensing a first substance and a second substance, the sensor comprising first (3) and second (5) sensor components each comprising a first material (20), the first material being sensitive to both the first substance and the second substance, the sensor further comprising a barrier (18) for preventing the second substance from passing into the second sensor component (5).Type: ApplicationFiled: July 16, 2010Publication date: October 18, 2012Applicant: NXP B.V.Inventors: Aurelie Humbert, Youri Victorovitch Ponomarev, Roel Daamen, Matthias Merz
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Patent number: 8288754Abstract: The present invention relates to a method for position-controlled fabrication of a semiconductor quantum dot, the method comprising: providing a substrate (102) of a substrate material; depositing a sacrificial layer (108) of a sacrificial material; depositing an active layer (110) of a semiconductive active material on the sacrificial layer, wherein the substrate, sacrificial and active materials are chosen such that the sacrificial layer is selectively removable with respect to the substrate and the active layer, depositing and patterning a mask layer on the active layer so as to define desired quantum-dot positions in lateral directions, fabricating a lateral access to the sacrificial layer in regions underneath the patterned mask layer; selectively removing, with respect to the substrate and the active layer, the sacrificial layer from underneath the active layer at least under the patterned mask layer; and etching the active layer under the patterned mask layer from underneath the active layer so as to aType: GrantFiled: March 11, 2009Date of Patent: October 16, 2012Assignees: NXP B.V., ST MicroElectronics (Crolles 2) SASInventors: Gregory Bidal, Frederic Boeuf, Nicolas Loubet
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Patent number: 8289077Abstract: An amplifier (A1) within a signal processor comprises a pair of complementary differential pairs (DP1, DP2) in the sense that one differential pair comprises transistors having a polarity opposite to that of transistors in the other differential pair. The one and the other differential pair commonly receive a differential input signal, which has a common mode component. A current combining circuit (CC) combines output currents of the one and the other differential pair so as to obtain an output current that varies as a function of the differential input signal. The one and the other differential pair each have a biasing circuit (R1, R2), which provides a tail current that varies with the common mode component in a substantially linear fashion.Type: GrantFiled: November 7, 2008Date of Patent: October 16, 2012Assignee: NXP B.V.Inventor: Paulus P. F. M. Bruin
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Publication number: 20120256645Abstract: A sensor for sensing an analyte includes capacitive elements, each having a pair of electrodes separated by a dielectric wherein the dielectric constant of the dielectric of at least one of the capacitive elements is sensitive to the analyte, the sensor further including a comparator adapted to compare a selected set of capacitive elements against a reference signal and to generate a comparison result signal, and a controller for iteratively selecting the set in response to the comparison result signal, wherein the sensor is arranged to produce a digitized output signal indicative of the sensed level of the analyte of interest. An IC comprising such a sensor, an electronic device comprising such an IC and a method of determining a level of an analyte of interest using such a sensor are also disclosed.Type: ApplicationFiled: April 3, 2012Publication date: October 11, 2012Applicant: NXP B.V.Inventors: Viet Hoang Nguyen, Roel Daamen, Axel Nackaerts, Pascal Bancken
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Publication number: 20120259188Abstract: Disclosed is a flexible insert (100) for placement on the human eye, comprising a light source (110) in said insert such that light emitted from the light source is shielded from the human eye upon correct placement of the insert on the human eye, a light-responsive material (120) placed in the light path of the light source, said light-responsive material emitting light upon stimulation by the light from said light source, the intensity of said stimulated emission being sensitive to a chemical interaction of the light-sensitive material with an analyte of interest, a photodetector (130) for detecting the light emitted by the light-responsive material; and a transmitter (140) coupled to the photodetector for transmitting a photodetector reading. The insert may be used in conjunction with a reader for automated monitoring of an analyte of interest such as glucose in the tear fluid of its wearer.Type: ApplicationFiled: March 30, 2012Publication date: October 11, 2012Applicant: NXP B.V.Inventor: Willem Frederik Adrianus Besling
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Publication number: 20120257655Abstract: A transceiver includes a transmit pin configured to receive a signal from a microcontroller, a receive pin configured to transmit a signal to the microcontroller, at least one bus pin configured to transmit and receive signalling to or from the network, a wake-up detector, an acknowledge and/or wake-up generator, and at least one switch is operable to put the transceiver in a first mode of operation. In the first mode of operation the transmit pin is connected to the wake-up detector, and the wake-up detector is configured to activate a wake-up code in accordance with configuration information received at the transmit pin, and the receive pin is connected to an acknowledge and/or wake-up generator, which is configured to provide an acknowledge and/or wake-up signal to the receive pin based on a comparison of actual configuration information stored in the transceiver with the received configuration information from the transmit pin.Type: ApplicationFiled: December 21, 2010Publication date: October 11, 2012Applicant: NXP B.V.Inventor: Matthias Muth
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Publication number: 20120260119Abstract: Various embodiments relate to an apparatus and associated method for a contactless front-end (CLF) managing a secure element (SE). When the SE receives a low power, a monitoring circuit in the CLF may monitor a power supplied to the SE. Upon detection of an under-voltage condition, the monitoring circuit may cause a management module in the CLF to react to the detected under-voltage condition with an SE management technique. The management module may enact the SE management technique through a separate communications interface connected to the SE. In some embodiments, the CLF may further comprise a register that maintains an under-voltage flag that is triggered when the monitoring circuit detects an under-voltage condition. The management module may reset the under-voltage flag and may use the triggering of the under-voltage flag one or more times to determine whether to react through use of a SE management technique.Type: ApplicationFiled: March 20, 2012Publication date: October 11, 2012Applicant: NXP B.V.Inventors: Nicolas Garnier, Xavier Kerdreux, Fabien Boitard
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Publication number: 20120256606Abstract: A multiple output switching circuit (300) comprising an input (302) configured to receive power from a power source; a first output (304) configured to provide a first output voltage; and an inductor (308) and a power switch (306) connected between the input (302) and first output (304). The power switch (306) is operable to transfer power from the input (302) to the first output (304). The switching circuit further comprising a second output (312) configured to provide a second output voltage; a second switch (310) coupled between the first output (302) and the second output (312); and a second switch controller (314) configured to provide the second switch (310) with a second switch control signal (318) such that power is transferred from the input (302) to the second output (312) when the first output voltage level reaches a first output threshold level.Type: ApplicationFiled: March 30, 2012Publication date: October 11, 2012Applicant: NXP B.V.Inventor: Leendert Albertus Dick van den Broeke
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Patent number: 8284608Abstract: A non-volatile memory circuit includes memory rows and supporting circuits coupled to the memory rows, where at least one of the memory rows include at least one Electrically Erasable Programmable Read-Only Memory (EEPROM) memory element and at least one Flash memory element. The EEPROM and Flash elements are configured to share some of the supporting circuits and can be accessed in parallel.Type: GrantFiled: October 5, 2010Date of Patent: October 9, 2012Assignee: NXP B.V.Inventors: Sönke Ostertun, Christoph Hans Joachim Garbe, Andreas Nentwig, Nils Sandersfeld
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Patent number: 8284823Abstract: A serial data communication system (10) comprises—a local clock generation device (12) adapted for generating a clock signal (16) with a duty cycle depending on a control signal (18), and—a serial data communication control device (14) adapted for generating the control signal (18) depending on the receipt of a serial data signal and for deriving a transmit and receive clock signal (20, 21) from the clock signal (16) received from the local clock generation device (12).Type: GrantFiled: December 14, 2006Date of Patent: October 9, 2012Assignee: NXP B.V.Inventor: Klemens Breitfuss
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Patent number: 8283975Abstract: A device (100) for processing an input signal (102), the device (100) comprising a delay unit (104) adapted for delaying the input signal (102) by a predefined delay time, at least one phase shifting unit (106) each adapted for phase shifting the delayed input signal (108) by an assigned phase value, a plurality of mixer units (110) each adapted for mixing the input signal (102) with the delayed input signal (108) or with one of the at least one phase shifted signal (112), and an extraction unit (114) adapted for extracting information from each of the mixed signals (116).Type: GrantFiled: March 9, 2009Date of Patent: October 9, 2012Assignee: NXP B.V.Inventors: Harald Witschnig, Franz Amtmann, Christian Patauner
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Patent number: 8285731Abstract: A road pricing smart client and method for a road pricing system enabling the removal of information from the positioning data describing the itinerary which suggest private data such as travelling speed and itinerary of the originator of the data. Accordingly, the smart client and method is configured to re-sample the original positioning points of the route into equidistant sections, remove timing information from the positioning data, slice the re-sampled route into slices shaped as those provided by other road users by employing a common “virtual grid”. By transmitting the slices in randomized order with an arbitrary delay, coherence of slices corresponding to formerly neighboring portions of the itinerary, are not correlated anymore. However, there is still enough information provided to the toll system to send an excerpt of the fee database allowing the smart pricing client or method to calculate the occurred fees.Type: GrantFiled: December 1, 2010Date of Patent: October 9, 2012Assignee: NXP B.V.Inventors: Michaël Michel Patrick Peeters, Claude Debast, Stefaan Motte
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Patent number: 8283947Abstract: A high voltage tolerant bus holder circuit and method of operating the bus holder circuit utilizes first and second control transistors connected in parallel between a control terminal of a pull-up transistor and a bus. The first control transistor is used to turn on the pull-up transistor during a pull-up mode of operation. The second control transistor is used to turn off the pull-down transistor when a voltage on the bus exceeds a threshold.Type: GrantFiled: June 3, 2011Date of Patent: October 9, 2012Assignee: NXP B.V.Inventors: Jayarama Ubaradka, Dharmaray M. Nedalgi
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Patent number: 8285037Abstract: Display driver (40) with a frame memory (43) for temporarily storing image data representing a color image and a data bus for feeding RGB-formatted image data to said display driver (40). The display driver (2) comprises means for performing an encoding decision process (42) that is based on an analysis of the nature of a pixel cluster of said image data. The means for performing a decision process (42) allow the display driver (43) to decide whether a first compression format or a second compression format is to be applied for compression of said pixel cluster. The first compression means (33.1) perform a compression of said pixel cluster into said first compression format (quantized RGB), and the second compression means (33.2) perform a compression of said pixel cluster into said second compression format (color compressed).Type: GrantFiled: February 22, 2006Date of Patent: October 9, 2012Assignee: NXP B.V.Inventors: Christopher R. Speirs, Matheus J. G. Lammers
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Patent number: 8283955Abstract: The present invention relates to a double data rate interface and method for use between a processor and random access memory, comprising a delay line including means for creating a delay in a data strobe signal from the random access memory, the delay line being arranged such that the delay in the data strobe signal is equal to the sum of set-up time and data bus rise time. The interface of includes the delay line comprising the delay locked loop which in turn comprises a ring oscillator. The ring oscillator includes a buffer and a Vernier delay.Type: GrantFiled: October 29, 2010Date of Patent: October 9, 2012Assignee: NXP B.V.Inventor: William Redman-White
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Patent number: 8284881Abstract: The present invention provides for method of seeking synchronization at a data interface between a transmitting element and a receiving element, and to related transmitting and receiving elements of the interface, in which the clock frequency of both elements is the same but which exhibit a phase difference, also known as mesochronous clock domains, the method including the steps of, prior to data transfer at the interface, delivering a strobe signal generated at the transmitting element to the receiving element, generating a strobe signal at the receiving element and synchronizing the same to the strobe signal received from the transmitting element, and maintaining the synchronized strobe signal generated at the receiving element for the sampling of data appearing at the interface from the transmitting element.Type: GrantFiled: October 30, 2006Date of Patent: October 9, 2012Assignee: NXP B.V.Inventors: Davy Witters, Jo Frisson, Steven De Cuyper, James Joseph McCormack
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Patent number: 8284879Abstract: Transfer circuits (200, 400, 500) for monitoring in a monitor clock domain target events that occur in a target clock domain (170) are disclosed. Some embodiments (200) impose significant constraints on the domain clocks and include: an event detector (210); a sending circuit (220) that changes the value of a request signal (150) with each event; and a receiving circuit (230) that detects changes in the request signal. Other embodiments work for a broader range of clocks and include: a counter (410) that generates an incremental count (415) of event occurrences while a transfer is taking place; sending and receiving registers (420, 430, 530) for the incremental count; the request sending and receiving circuits (220, 230), where the request signal changes value for each transfer of the incremental count; and sending and receiving circuits (470, 480) for an acknowledgement signal.Type: GrantFiled: June 25, 2004Date of Patent: October 9, 2012Assignee: NXP B.V.Inventors: Otto Steinbusch, Marino Strik, Robert De Gruijl
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Publication number: 20120249112Abstract: A switched mode power supply (SMPS) controller is disclosed. The controller comprises a monitoring circuit adapted to monitor the rate of change of a voltage at an input (1) and to monitor the drop in voltage at the input (1) from a peak value. The controller is adapted to generate a signal for closing the switch when the monitored rate of change falls below a first predetermined threshold and the monitored drop in voltage exceeds a second predetermined threshold.Type: ApplicationFiled: March 28, 2012Publication date: October 4, 2012Applicant: NXP B.V.Inventor: Wilhelmus Hinderikus Maria LANGESLAG
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Publication number: 20120252361Abstract: Various exemplary embodiments relate to a radio frequency identification chip or a near-field communication chip having a wireless interface, a buffer, and a wired interface. A microcontroller may be connected to the wired interface. The radio frequency identification chip may receive customization data via the wireless interface, temporarily store the customization data in the buffer, and transmit the customization data to the microcontroller via the wired interface. The customization data may include data for a specific region, language, or model of consumer electronic product.Type: ApplicationFiled: March 31, 2011Publication date: October 4, 2012Applicant: NXP B.V.Inventors: Gunter STROMBERGER, Thomas Fina