Patents Assigned to NXP
  • Publication number: 20120249191
    Abstract: In one aspect, a buffer circuit comprises a source or emitter follower input stage and output stage. A load is provided between the stages which comprises a representation of an output load of the buffer circuit. This improves the circuit linearity whilst enabling a high input impedance to be obtained. In another aspect, a buffer circuit comprises a source or emitter follower output stage. A load is in the form of a filter is provided and which comprises a representation of an output load of the buffer circuit.
    Type: Application
    Filed: March 27, 2012
    Publication date: October 4, 2012
    Applicant: NXP B.V.
    Inventors: Herve Marie, Lionel Guiraud
  • Publication number: 20120249308
    Abstract: A method for handling collision in an identification system where the identification system includes a reader, a first transponder and a second transponder. The method involves the reader transmitting an initialization command to the first transponder and to the second transponder; upon receiving the initialization command, the first transponder and the second transponder enter into a muted state where the first transponder and the second transponder do not respond to commands from the reader; in a randomly determined first start time slot the first transponder enters into an un-muted state and the first transponder remains in the un-muted state until the reader sends a mute command to the first transponder; in a randomly determined second start time slot the second transponder enters into an un-muted state and the second transponder remains in the un-muted state until the reader sends a mute command to the second transponder.
    Type: Application
    Filed: February 9, 2012
    Publication date: October 4, 2012
    Applicant: NXP B.V.
    Inventor: Juergen Nowottnick
  • Publication number: 20120250401
    Abstract: A phase change memory (PCM) architecture and a method for writing a PCM architecture are described. In one embodiment, a PCM architecture includes a PCM array, word line driver circuits, bit line driver circuits, a source driver circuit and a voltage supply circuit. The bit line driver circuits are connected to the PCM array and the electrical ground. Other embodiments are also described.
    Type: Application
    Filed: March 29, 2011
    Publication date: October 4, 2012
    Applicant: NXP B.V.
    Inventors: Maurits Mario Nicolaas Storms, Erik Maria van Bussel, Godefridus Adrianus Maria Hurkx, Michiel Jos van Duuren
  • Publication number: 20120249168
    Abstract: Disclosed is a liquid immersion sensor comprising a substrate (10) carrying a conductive sensing element (20) and a corrosive agent (30) for corroding the conductive sensing element, said corrosive agent being immobilized in the vicinity of the conductive sensing element and being soluble in said liquid.
    Type: Application
    Filed: November 29, 2010
    Publication date: October 4, 2012
    Applicant: NXP B.V.
    Inventors: Aurelie Humbert, Matthias Merz, Roel Daamen, Youri Victorovitch Ponomarev
  • Publication number: 20120248570
    Abstract: A semiconductor chip has an integrated inductor, manufactured during back end of line processing. In particular, a loop (30) is formed in a metallization layer and a central region (32) of magnetic material is provided within the loop. The size of the central region is controlled so that it includes no more than five magnetic domains to achieve the desired properties.
    Type: Application
    Filed: December 14, 2010
    Publication date: October 4, 2012
    Applicant: NXP B.V.
    Inventors: Dusan Golubovic, Kyriaki Fotopoulou
  • Publication number: 20120249234
    Abstract: A receiver (400; 500) comprising an amplifier (406; 506) having an input (408) and an output (410). The input (408) of the amplifier is configured to receive a signal. The receiver also comprises a feedback path (412; 512) between the output (410) and the input (408) of the amplifier (406; 506), wherein the feedback path (412; 512) includes a filter (402; 502) and a buffer amplifier (414; 514) in series. The input of the buffer amplifier (414; 514) is connected to the output (410; 510) of the amplifier (406; 506). The output of the buffer amplifier (414; 514) is connected to the input of the filter (402; 502). The output of the filter (402; 502) is connected to the input (408; 508) of the amplifier (406; 506). The filter (402; 502) is configured to pass signals having a desired frequency.
    Type: Application
    Filed: March 29, 2012
    Publication date: October 4, 2012
    Applicant: NXP B.V.
    Inventors: Sebastien ROBERT, Walter JAUDARD
  • Publication number: 20120250200
    Abstract: A triac circuit comprises a triac having first and second main terminals (MT1,MT2) and a gate terminal and a thyristor connected between one of the main terminals (MT1,MT2) and a control terminal of the triac circuit. The thyristor is used to prevent turn on of the triac when it has turned on by temperature induced leakage currents.
    Type: Application
    Filed: March 29, 2012
    Publication date: October 4, 2012
    Applicant: NXP B.V.
    Inventors: Nick Ham, Ed Huang, Jianfeng Zhang, Andrew Mark Warwick, Andrew Butler, Minghao Jin
  • Publication number: 20120247707
    Abstract: An active thermal management device and method, in which a phase change material unit, comprising at least one phase change material arranged in series or parallel, is connectable to a source of thermal energy, such as LEDs at a first operating condition. Thermal energy from the source of thermal energy is stored in the phase change material unit. The phase change material unit is connectable to a sink of thermal energy, such as second LEDs at a second operating condition. The thermal energy stored in the phase change material unit may be re-used. The first operating condition can include a 15V supply voltage, and the second operating condition can include either no supply voltage, or a lower 9V supply voltage of 9V, such that heat from the first LEDs, which may be over-temperature, can pre-heat the second LEDs, improving thermal and optical matching.
    Type: Application
    Filed: March 20, 2012
    Publication date: October 4, 2012
    Applicant: NXP B.V.
    Inventors: Radu Surdeanu, Damien Lenoble
  • Publication number: 20120249265
    Abstract: A resonator comprising a resonator body and actuation electrodes for driving the resonator into a resonant mode, in which the resonator body vibrates parallel to a first axis. The resonator comprises means to apply a voltage to the resonator in a direction perpendicular to the first axis direction. This serves to shift the frequency of resonant modes other than the principal resonant mode, and this allows increased amplitude of output signal from the resonator.
    Type: Application
    Filed: March 26, 2012
    Publication date: October 4, 2012
    Applicant: NXP B.V.
    Inventors: Casper van der Avoort, Andreas Bernardus Maria Jansman
  • Publication number: 20120248575
    Abstract: The present invention provides a semiconductor with a multilayered contact structure. The multilayered structure includes a metal contact placed on an active region of a semiconductor and a metal contact extension placed on the metal contact.
    Type: Application
    Filed: December 21, 2009
    Publication date: October 4, 2012
    Applicant: NXP B.V.
    Inventors: Soenke Habenicht, Detief Oelgeschlaeger, Olrik Schumacher, Stefan Bengt Berglund
  • Publication number: 20120250768
    Abstract: Video decoder apparatus and method, for decoding a motion-compensated transform-coded video stream. The apparatus has: a first mode in which it is operable to decode the video stream at a first resolution, and wherein a motion-compensation step of the decoding is performed in the image-domain. It also has a second mode in which it is operable to decode the video stream at a second resolution, and wherein at least one motion-compensation step is performed in the transform-domain. The decoder is adapted to switch between the two modes while decoding the video stream.
    Type: Application
    Filed: March 23, 2012
    Publication date: October 4, 2012
    Applicant: NXP B.V.
    Inventors: Manivel Sethu, Francois Martin, Pradeep Muruganandam, Sudeendra Maddur Gundurao
  • Patent number: 8280329
    Abstract: A receiver has an input amplifier (RFAMP) that comprises a signal-voltage amplifier (SVA) and a feedback path (FBP). The signal-voltage amplifier (SVA) provides a voltage gain (VG) from an input node (SESf) to an output node (SON). The voltage gain (VG) is controllable. The feedback path (FBP) provides a transadmittance (GM) from the output node (SON) to the input node (SIN). The transadmittance (GM) is controllable.
    Type: Grant
    Filed: March 3, 2006
    Date of Patent: October 2, 2012
    Assignee: NXP B.V.
    Inventor: Frederic Mercier
  • Patent number: 8281197
    Abstract: A method (200) for locating a fault in an integrated circuit (100) having a plurality of digital outputs coupled to compaction logic (140) in a test mode of the integrated circuit, the compaction logic comprising at least one output for providing a test response is disclosed. The method comprises the steps of: providing a simulation model of the integrated circuit (210); providing the simulation model with a plurality of test patterns (220); receiving a plurality of simulated test responses to said test patterns (230); defining a plurality of bits in the plurality of responses, said bits defining a signature of the fault (240); providing the integrated circuit with a further plurality of test patterns (250); receiving a plurality of test responses to said further plurality of test patterns (260); and checking the plurality of responses for the presence of the signature (270). This method provides improved fault detectability for an IC subjected thereto.
    Type: Grant
    Filed: October 23, 2006
    Date of Patent: October 2, 2012
    Assignee: NXP B.V.
    Inventor: Hendrikus Petrus Elisabeth Vranken
  • Patent number: 8280326
    Abstract: A receiver comprises a radio frequency splitter and respective tuning elements, which are coupled to respective outputs of the radio frequency splitter One of these tuning elements has a control terminal coupled to receive a direct current control signal via a radio frequency-blocking circuit. A direct current path extends, via the radio frequency splitter, from the aforementioned control terminal to a control terminal of another tuning element.
    Type: Grant
    Filed: April 17, 2007
    Date of Patent: October 2, 2012
    Assignee: NXP B.V.
    Inventors: Thomas Fenkes, Klaus Bracht
  • Patent number: 8280333
    Abstract: A harmonic rejection mixer unit is provided which comprises an input (RF), at least one harmonic rejection unit (HRU) with at least two transistor units (T3a, T3b; T4a, T4b) for multiplying an input signal from the input (RF) with a multiplication signal (ELO). The harmonic rejection mixer unit furthermore comprises a transistor control signal generating unit (GGU) for generating transistor control signals (GS1-GS4) for the at least two transistor units (T3a, T3b; T4a, T4b) of the at least one harmonic rejection unit (HRU) by deriving the transistor control signals (GS1-GS4) from a local oscillator signal (LO). The transistor control signals (GS3, GS4) for the at least two transistor units (T3a, T3b; T4a, T4b) are generated with a duty cycle of <50% and are generated such that the shape of the multiplication signal ELO) is achieved by a constructive summation of the output signals from the transistor units (T3a, T3b; T4a, T4b).
    Type: Grant
    Filed: July 30, 2008
    Date of Patent: October 2, 2012
    Assignee: NXP B.V.
    Inventors: Jan Van Sinderen, Sebastien Amiot, Leonardus H. M. Hesen
  • Patent number: 8278202
    Abstract: A method for manufacturing on a substrate a semiconductor device with a floating-gate and a control-gate. The method includes the steps of first forming an isolation zone in the substrate, and thereafter forming the floating gate on the substrate. The method further includes extending the floating gate using spacers, and then forming the control gate over the floating gate and the spacers.
    Type: Grant
    Filed: July 21, 2008
    Date of Patent: October 2, 2012
    Assignee: NXP B.V.
    Inventors: Antonius Maria Petrus Johannes Hendricks, Josephus Franciscus Antonius Maria Guelen, Guido Jozef Maria Dormans
  • Patent number: 8278900
    Abstract: A power supply includes a PFC stage 6 and an SMPS stage 8. The power supply can operate in a normal mode in which the PFC stage supplies a voltage to the SMPS stage. In a standby mode, the PFC stage is operated in bursts to supply a lower voltage to the SMPS stage that is high enough that the SMPS stage can rapidly respond when it needs to supply a load.
    Type: Grant
    Filed: January 5, 2006
    Date of Patent: October 2, 2012
    Assignee: NXP B.V.
    Inventors: Arjan Strijker, Gerrit Terpstra, Wilhelmus H. M. Langeslag
  • Patent number: 8279635
    Abstract: A driving circuit for an opto-coupler comprising a switched mode regulator configured to convert a first voltage to a second voltage, the switched mode regulator operable in accordance with a control signal (311) representative of the first voltage, and wherein the second voltage is used to drive the diode (304a) of the opto-coupler (304), in use.
    Type: Grant
    Filed: July 28, 2010
    Date of Patent: October 2, 2012
    Assignee: NXP B.V.
    Inventor: Joan Wichard Strijker
  • Patent number: 8280304
    Abstract: A device and a method for programming the read/writeable memory of the RFID circuitry by communications between either RF antenna (12) or bus communications port controller interface (4) or both. In a peripheral device (1), an EEPROM (6), bus communications controller interface (4), NFC interface (8), antenna (12), and logic controller (10) operate to receive and transmit configuration and calibration data between a Bluetooth circuit (40) and an external device (22). The dual interfaced EEPROM (2) shares or partitions its EEPROM (6) between the Bluetooth circuit (40) and the external device (22).
    Type: Grant
    Filed: August 15, 2007
    Date of Patent: October 2, 2012
    Assignee: NXP B.V.
    Inventor: Olaf Hirsch
  • Patent number: 8279005
    Abstract: There is provided a method and apparatus for maintaining a bias current that flows through two transistors at a target level. The two transistors are both connected to form a series network between positive and negative voltage supply terminals. The bias current flows through the two transistors when the circuit is at equilibrium, and the threshold voltage of the transistors is controlled by controlling the voltage that is applied to the transistors bulk terminals. In addition to the two transistors, there is provided a control circuit that measures a circuit parameter that is indicative of the level of bias current flowing through the two transistors. In response to the measured parameter, the control circuit adjusts the bulk voltage levels of the two transistors so as to alter the transistors threshold voltages and maintain the level of bias current at a target level.
    Type: Grant
    Filed: March 18, 2008
    Date of Patent: October 2, 2012
    Assignee: NXP B.V.
    Inventors: Johannes H. A. Brekelmans, Lorenzo Tripodi