Abstract: An isolation region (14) is formed between an edge termination region (2) having deep trenches (20,34) and the central region (4). The isolation region includes gate fingers (18) extending from the edge gate trench regions (28) to the gate trenches (6) in the central region (4) to electrically connect the edge gate trench regions to the gate trenches (6) in the central region. The isolation region also includes isolation fingers (22,24) extending from the edge termination region (2) towards the central region (4) and gate between the gate fingers (18) for reducing the breakdown voltage with a RESURF effect.

Abstract: A method of manufacturing a heterojunction bipolar transistor, including providing a substrate comprising an active region bordered by shallow trench insulation regions; depositing a stack of a dielectric layer and a polysilicon layer over the substrate; forming a base window in the stack, the base window extending over the active region and part of the shallow trench insulation regions, the base window having a trench extending vertically between the active region and one of the shallow trench insulation regions; growing an epitaxial base material inside the base window; forming a spacer on the exposed side walls of the base material; and filling the base window with an emitter material. A HBT manufactured in this manner and an IC including such an HBT.

Abstract: Various embodiments relate to a multi-standard Viterbi decoder. Based on programmable values for constraint length, generator polynomials, and code rate, the multi-standard Viterbi decoder may adhere to a specific convolutional code standard. At a given time, the multi-standard Viterbi decoder may receive a variety of convolutional codes through a channel and may process them using various forms of the trace back method. Various embodiments include a branch metric unit and path metric unit that include a variety of sub-units that may or may not be active based on the value of the programmable value. Various embodiments also enable the multi-standard Viterbi decoder to handle different forms of convolutional codes, such as tail-biting codes. In some embodiments, the multi-standard Viterbi decoder may also process at least two convolutional codes concurrently.

Abstract: Disclosed is a method of manufacturing a vertical bipolar transistor in a CMOS process, comprising implanting an impurity of a first type into a the substrate (100) to form a buried region (150, 260) therein; forming a halo implant (134) using an impurity of a second type and a shallow implant (132) using an impurity of the first type, said halo implant enveloping the shallow implant in the substrate and being located over said buried region (150, 250); forming, adjacent to the halo implant (134), a further implant (136) using an impurity of the second type for providing a conductive connection to the halo implant; and providing respective connections (170, 160, 270) to the further implant (136), the shallow implant (132) and the buried region (150, 260) allowing the shallow implant, halo implant and buried region to be respectively operable as emitter, base and collector of the vertical bipolar transistor.

Abstract: A signal level adjusting device (AD), for RF communication equipment arranged to received primary RF signals, comprises i) a tuner (TU) comprising a gain control means (SI,R), arranged to define a first or second digital command signal respectively each time it receives a first or second digital control signal respectively, and a gain adjusting means (VGA) arranged to decrease or increase respectively its gain by a fixed value when the command signal defined by the gain control means (SI,R) is a first or second command signal respectively, in order to adjust the level of the received primary RF signals, and ii) a demodulator (DEM) comprising a level control means (LCM1) arranged to generate a first or second digital control signal respectively each time it detects an increase or decrease respectively of the level of secondary signals representative of the adjusted signals output by the tuner (TU).

Abstract: An apparatus and method for supporting PCI Express is disclosed. A physical layer has a PCI Express interface for receiving data from a PCI Express compatible communication medium. The data is in the form of a packet. A data link layer is disclosed for verifying a CRC value and a sequence number received within the packet. A transaction layer is disclosed for receiving the packet from the data link layer and for processing thereof. The transaction layer processes at least some of the packet data in parallel to the data link layer.

Abstract: The electric device according to the invention has a resistor comprising a layer of a phase change material which is changeable between a first phase with a first electrical resistivity and a second phase with a second electrical resistivity different from the first electrical resistivity. The phase change material is a fast growth material. The electric device further comprises a switching signal generator for switching the resistor between at least three different electrical resistance values by changing a corresponding portion of the layer of the phase change material from the first phase to the second phase.

Abstract: An electronic device is made from a first substrate with device circuitry including an inductor and a second substrate with inductance adjustment circuitry including a number of other inductors. The substrates are assembled together to be opposite one another. The other inductors are arranged to provide a selection of different mutual inductance relationships relative to the inductor. These relationships are selectable during operation of the device to provide a variable inductance in the device circuitry.

Abstract: The invention relates to a method of manufacturing a semiconductor device with a substrate and a semiconductor body, whereby in the semiconductor body a semiconductor element is formed by means of a mesa-shaped protrusion of the semiconductor body, which is formed on the surface of the semiconductor device as a nano wire, whereupon a layer of a material is deposited over the semiconductor body and the resulting structure is subsequently planarized in a chemical-mechanical polishing process such that an upper side of the nano wire becomes exposed. According to the invention, a further layer of a further material is deposited over the semiconductor body with the nano wire before the layer of the material is deposited, which further layer is given a thickness smaller than the height of the nano wire, and a material is chosen for the further material such that, viewed in projection, the transition between the layer and the further layer is discernible before the nano wire is reached.

Abstract: A piezoresistive MEMS oscillator comprises a resonator body, first and second drive electrodes located adjacent the resonator body for providing an actuation signal; and at least a first sense electrode connected to a respective anchor point. The voltages at the electrodes are controlled and/or processed such that the feedthrough AC current from one drive electrode to the sense electrode is at least partially offset by the feedthrough AC current from the other drive electrode to the sense electrode.

Abstract: The invention relates to a device for compensating influence of temperature on a resonator circuit. The device comprises a resonator circuit and a supply unit for supplying an electric bias signal to the resonator circuit, wherein the supply unit is adapted for adjusting the electric bias signal for compensating influence of temperature on the resonator circuit.

Abstract: The invention relates to a pointing device and a method for processing signals from such a pointing device, said device comprising a base and an actuator movable with respect to the base, and a detector, said detector adapted for providing at least first and second positional signals indicating a position of the actuator with respect to the base along corresponding first and second axes, wherein said signal processing method comprises the steps of converting the at least two positional signals into a polar coordinate signal comprising a magnitude signal, and thresholding the magnitude signal of the polar coordinate signal to provide a thresholded magnitude signal. In an embodiment the method further comprising the step of applying a conversion curve to the thresholded magnitude signal to produce a velocity magnitude signal.

Abstract: A multimode receiver has a transconductance amplifier having an input terminal and adapted to receive a voltage RF signal and to deliver a current RF signal. The amplifier has a current mixer coupled to the transconductance amplifier and adapted to receive the current RF signal, the current mixer being adapted to combine the current RF signal with a signal generated by a local oscillator, the mixer generating an intermediate frequency signal having a frequency that equals a combination of a frequency of the current RF signal and a frequency of the local oscillator. A low-pass filter is coupled to the mixer and is adapted to generate a low-pass current signal. A transimpedance amplifier is coupled to the low-pass filter and is adapted to receive the low-pass current signal, the transimpedance amplifier being adapted to generate an intermediate frequency voltage signal proportional with the low-pass current signal.

Abstract: A shrinking-pulse digital delay line (400) has a cascade of a plurality of stages (102,104) for modifying a width of a pulse propagating down the cascade (106 to 118). Each specific one of the stages has an input (106,116), an output (108,118) and a main path (110,112,120,122) between the input and the output. The main path has a first inverter (110,120) and a second inverter (112,122) connected in series via an intermediate node (114,124). Each specific stage has a third inverter (128,140) connected between the input and the intermediate node of a downstream stage in the cascade (102,104); and also has a fourth inverter (132,144) connected between the intermediate node of the specific stage (mode 114, stage 102, mode 124, stage 104) and the output (118, stage 104) of the downstream stage (stage 104).

Abstract: Various embodiments relate to a system and related method that enable transfer of control and data messages in a wireless communication network between devices operating on different physical layers (PHY). Control data and/or isochronous data and/or asynchronous data may be transferred between devices that operate on different physical layers through a bridging device, while minimizing latency and buffering. The bridging device may contain interfaces that may operate on each of the respective physical layers. A first interface may receive a first superframe from a device in a first physical layer (PHY1) and may generate an equivalent second superframe to transmit to a second device on a second physical layer (PHY2). The bridging device may also synchronize the time slots and reference clocks for communication protocols on each physical layer to further minimize latency and buffering during the transfer of control and data messages via communication frames within these superframes.

Abstract: The invention relates to a method for manufacturing a micromachined microphone and an accelerometer from a wafer 1 having a first layer 2, the method comprising the steps of dividing the first layer 2 into a microphone layer 5 and into an accelerometer layer 6, covering a front side of the microphone layer 5 and a front side of the accelerometer layer 6 with a continuous second layer 7, covering the second layer 7 with a third layer 8, forming a plurality of trenches 9 in the third layer 8, removing a part 10 of the wafer 1 below a back side of the microphone layer 5, forming at least two wafer trenches 11 in the wafer 1 below a back side of the accelerometer layer 6, and removing a part 12, 13 of the second layer 7 through the plurality of trenches 9 formed in the third layer 8. The micromachined microphone and the accelerometer according to the invention is advantageous over prior art as it allows for body noise cancellation in order to minimize structure borne sound.

Abstract: A method of manufacturing a semiconductor device (1200), the method comprising forming a sacrificial pattern having a recess on a substrate (402), filling the recess and covering the substrate and the sacrificial pattern with a semiconductor structure, forming an annular trench in the semiconductor structure to expose a portion of the sacrificial pattern and to separate material (904) of the semiconductor structure enclosed by the annular trench from material (906) of the semiconductor structure surrounding the annular trench, removing the exposed sacrificial pattern to expose material of the semiconductor structure filling the recess, and converting the exposed material of the semiconductor structure filling the recess into electrically insulting material (1202).

Abstract: An IC (100) for communicating over a data communication bus (220) comprising a first pair of conductors including a data signal conductor (SDA) and a synchronization signal conductor (SCL), e.g. an I2C bus, is disclosed. The IC comprises a group of address pins (106a-c) for defining the bus address of the integrated circuit (100), each address pin being arranged to be coupled to a conductor from a group of conductors comprising the first pair of conductors and a second pair of conductors including a conductor for carrying a fixed high potential (Vdd) and a conductor for carrying an fixed low potential (GND).

Abstract: An RFID device (100) being operable in a first and a second operating state, the RFID device comprises a control unit (102), wherein the control unit comprises a configuration input terminal for receiving a configuration signal, and a processing unit (101), which is coupled to the control unit, wherein the control unit is adapted for switching the processing unit between the first and the second operating state based on the configuration signal, wherein the control unit (102) comprises an activation input terminal for receiving an activation signal.

Abstract: A magnetoresistive sensor comprising first and second magnetoresistive elements is disclosed. Each magnetoresistive element is coupled at a respective first end to a common ground terminal and comprises one or more magnetoresistive segments, each overlying a corresponding segment of an excitation coil. The resistance of the magnetoresistive segments in each of the first and second magnetoresistive elements is the same and the resistance of the segments of the excitation coil corresponding to the first magnetoresistive element is the same as the resistance of the segments of the excitation coil corresponding to the second magnetoresistive element.