Patents Assigned to NXP
  • Publication number: 20120014465
    Abstract: A linear iterative channel estimation scheme and corresponding pilot allocation scheme are provided to perfect a channel model that cancels the Inter-Carrier Interference (ICI) for multi-carrier systems (e.g., OFDM, SC-FDMA, MC-CDMA, etc.) under high mobility conditions. Two issues of the linear iterative channel estimation scheme of the channel model, namely, overloaded pilots and increased Gauss noise are specifically addressed by exemplary embodiments. With the iterative channel estimation scheme provided by the present invention, the minimum pilot number is equal to the length of multi-path delay, and the Gauss noise is not increased.
    Type: Application
    Filed: August 4, 2008
    Publication date: January 19, 2012
    Applicant: NXP B.V.
    Inventors: Xiabo Zhang, Ni Ma
  • Publication number: 20120014146
    Abstract: A method and controller for power dependant mains under-voltage (“brown-out”) protection is disclosed. Brown-out protection is meant for protection against overheating due to low mains voltage and associated high mains current. Usually this is coupled to the absolute value of the mains voltage, but for devices operating at low power this is not necessary, as overheating will not occur. The disclosed method and controller allow for lower mains voltages at low load by comparing the mains voltage with a signal indicating the actual power level of the power supply. In converters such as flyback converters, this brown-out protection can be implemented by comparing the actual peak voltage of the mains voltage with a control signal that indicates the power level, such as the current through the optocoupler in the feedback loop.
    Type: Application
    Filed: July 14, 2011
    Publication date: January 19, 2012
    Applicant: NXP B.V.
    Inventor: Frans Pansier
  • Patent number: 8097091
    Abstract: There is an apparatus for cleaning a substrate (5) mounted on a moveable platen. In an example embodiment, the apparatus comprises a first chamber (20), the first chamber has solvent-dispensing nozzles (25); the solvent-dispensing nozzles wet the substrate surface (5) with a solvent (7) as the platen transports the substrate. The platen moves in a predetermined direction and at a predetermined scan velocity as it transports the substrate into a process chamber. The process chamber has a hot source (30) at a predetermined height (h) from the substrate surface (5); it provides heat energy directed toward the substrate surface, the heat energy evaporates the solvent (7) dispensed on the substrate surface; the solvent evaporation removes particulates (35) from the substrate surface, as the platen transports the substrate from the first chamber (20) into the process chamber. Substrates cleaned may include precision photo-masks, or wafers.
    Type: Grant
    Filed: August 23, 2005
    Date of Patent: January 17, 2012
    Assignee: NXP B.V.
    Inventors: Abbas Rastegar, Andy Ma, Dave Krick, Pat Marmillion
  • Patent number: 8099533
    Abstract: The present invention relates to a data processing system based on a multithreaded operating system. The data processing system comprises at least one processor (PROC) for processing data based on multiple threads, at least one controller unit (CU) for controlling the communication between said at least one processor (PROC) and an external peripheral device (PD) connected to said at least one controller unit (CU). Said at least one controller unit (CU) comprises at least one buffer memory (BM) for buffering data from said peripheral device (PD) connected to said at least one controller unit (CU), and at least one memory managing unit (MMU) for managing the access to said at least one buffer memory (BM) by mapping said at least one buffer memory (BM) into N banks (C0-C3) each with a dedicated prefetch register (Addr.0-Addr.3). At least one of said multiple threads (T0-T3) is mapped to one of said N banks (C0-C3) and its dedicated prefetch register (Addr.0-Addr.3).
    Type: Grant
    Filed: July 22, 2005
    Date of Patent: January 17, 2012
    Assignee: NXP B.V.
    Inventors: Chee Yu Ng, Nitin Satishchandra Kabra
  • Patent number: 8097535
    Abstract: The present invention relates to a semiconductor device with nanowire-type interconnect elements and a method for fabricating the same. The device comprises a metal structure with at least one self-assembled metal dendrite and forming an interconnect element (424) between a first and a second metal structure.
    Type: Grant
    Filed: August 31, 2007
    Date of Patent: January 17, 2012
    Assignee: NXP B.V.
    Inventors: Kevin Cooper, Srdjan Kordic
  • Patent number: 8097521
    Abstract: An electronic device (ICD) comprises an integrated circuit (AIC) and a capacitance element (PIC). The integrated circuit (AIC) is provided with a plurality of circuit contact pairs (CI). The capacitance element (PIC) is provided with a plurality of capacitance contact pairs (CC). A capacitance is present between each of at least part of the capacitance contact pairs (CC). The plurality of capacitance contact pairs (CC) faces the plurality of circuit contact pairs (CI). At least a part of the capacitance contact pairs (CC) is electrically coupled in a pair-by-pair manner to at least a part of the circuit contact pairs (CI).
    Type: Grant
    Filed: June 15, 2010
    Date of Patent: January 17, 2012
    Assignee: NXP B.V.
    Inventor: Joop Van Lammeren
  • Patent number: 8097949
    Abstract: The present invention relates to a method for fabricating an interconnect stack of an integrated-circuit device. Air gaps are fabricated in the interconnect stack on one or more interconnect levels. The method comprises forming local etch vias (216, 218) between a lower etch-barrier layer (236) and an upper etch-barrier layer (211) on top of an upper-intermediate interconnect level (224). Lateral inhomogeneities of the dielectric constant on the upper-intermediate interconnect level are removed in comparison with prior-art devices. For in the finished interconnect stack local variations in the dielectric permittivity can only occur at the (former) etch vias, which are either visible by the presence of air cavities or hardly visible due to a later filling with the dielectric material of the next interlevel dielectric layer.
    Type: Grant
    Filed: March 21, 2007
    Date of Patent: January 17, 2012
    Assignees: NXP B.V., Commissariat a l'Energie Atomique
    Inventors: Laurent Gosset, Jean Raymond Jacques Marie Pontcharra, Frederic Gaillard
  • Patent number: 8099614
    Abstract: The invention relates to a controlled shut-down of an electronic circuit or circuits such that the electrical power consumption of that circuit or circuits is minimized and that each said circuit is at a status which is a pre-determined state (42; 52) of that said circuit wherein all of its own control and messaging signals are taken to their zero level. The present invention claimed relates to the methodology of entering said circuit into this pre-determined state (42;52); where all said signal and messaging lines are taken to zero; thereby reducing power consumption within an electronic circuit when its status is defined as being shut-down or standby.
    Type: Grant
    Filed: September 11, 2006
    Date of Patent: January 17, 2012
    Assignee: NXP B.V.
    Inventors: Tim Pontius, Swati Saxena, Neal Wingen, Niranjan A. Puttaswamy
  • Publication number: 20120009873
    Abstract: In a method for transmitting an NFC application (9), a secure channel (14) is establishing by means of a proxy (11) between a Trusted Service Manager (1) and an NFC device (3) via a computing device (10) comprising the proxy (11) and via an RFID reader (12) being a part of the computing device (10). The NFC application (9) received at the computing device (10) from the Trusted Service Manager (1) is channeled through the secure channel (14) to the NFC device (3) utilizing the proxy (11).
    Type: Application
    Filed: February 24, 2010
    Publication date: January 12, 2012
    Applicant: NXP B.V.
    Inventors: Alexandre Corda, Baptiste Affouard
  • Publication number: 20120008722
    Abstract: A processor (110) is disclosed for processing a plurality of Fourier-transformed instances of a symbol, each instance being comprised in one of a plurality of frequency-divided multiplexed subcarriers, said processor being arranged to estimate, for each instance, the channel gain and the inter-carrier interference contribution to said symbol from neighboring subcarriers due to a time-varying channel response of the received signal, and combine the instances into a single representation of said symbol based on the estimated channel gain and the inter-carrier interference contributions. A receiver comprising such a processor and a method for processing such signals are also disclosed.
    Type: Application
    Filed: March 19, 2010
    Publication date: January 12, 2012
    Applicant: NXP B.V.
    Inventors: Semih Serbetli, Andries Pieter Hekstra
  • Publication number: 20120008717
    Abstract: The invention relates to frequency conversion systems, in particular for use as up-converters or down-converters in radiofrequency (RF) receivers or transmitters, exemplary embodiments including a radiofrequency receiver (1000) comprising: an RF signal input (1001); a mixing module (1002) comprising a first plurality of IF amplifiers (10041-3) each connected to the RF signal input (1001) via a switch (10031-3); a multi-phase local oscillator signal generator (1300) configured to provide a switching signal to each switch (10031-3); and a summing module (1005) configured to receive output signals from each of the IF amplifiers (10041-3) and to provide a second plurality of output IF signals from a weighted sum of the IF amplifier output signals, wherein the second plurality is different to the first plurality.
    Type: Application
    Filed: July 8, 2011
    Publication date: January 12, 2012
    Applicant: NXP B.V.
    Inventors: Jan van Sinderen, Johannes Hubertus Antonius Brekelmans, Frank Harald Erich Ho Chung Leong, Nenad Pavlovic
  • Publication number: 20120008350
    Abstract: For many applications an SMPS is designed to operate in boundary conduction mode. As the load decreases the switching frequency increases, and so the concept of valley skipping may be used in which the switching frequency is clamped, by delaying to turn on the time of the active switch, for an integral number of cycles of a resonant circuit in the SMPS. With further reduction of the load, additional valleys may be skipped. However, each change in the number of valleys skipped results in a step in the input current that is drawn, distorting the ideal mains sine wave, thereby increasing unwanted harmonics. Consistent with an example embodiment, there is a control method which reduces the steps: instead of a constant on-time for the switch, the duration of the on-time is increased each time an additional valley to be skipped.
    Type: Application
    Filed: November 30, 2010
    Publication date: January 12, 2012
    Applicant: NXP B.V.
    Inventors: Johann Baptist Daniel KUEBRICH, Thomas Antonius DUERBAUM, Hans HALBERSTADT
  • Publication number: 20120011228
    Abstract: In a method for processing top-up data, a server (8) receives data related to a request for issuing an NFC application (9). The data were sent by an NFC mobile device (3) and are intended for a Service Provider (2). At the server (8) transformed data are generated by transforming the data related to the request into a format complying with the Server Provider (2). The transformed data are sent to the Service Provider (2) for further processing and issuing the NFC application (9) to the mobile device (3) particularly utilizing a Trusted Service Manager (1).
    Type: Application
    Filed: February 25, 2010
    Publication date: January 12, 2012
    Applicant: NXP B.V.
    Inventors: Alexandre Corda, Vincent Lemonnier, Baptiste Affouard
  • Patent number: 8093097
    Abstract: A layer sequence (400), comprising an aluminum layer (300), a nickel layer (301), and a nickel layer protection layer (302; 701). The aluminum layer (300) is formable on a substrate (200), the nickel layer (301) is formed on the aluminum layer (300), and the nickel layer protection layer (302; 701) is formed on the nickel layer (301).
    Type: Grant
    Filed: June 12, 2006
    Date of Patent: January 10, 2012
    Assignee: NXP B.V.
    Inventors: Thomas Lange, Joerg Syre, Michael Rother, Torsten Krell
  • Patent number: 8093659
    Abstract: The invention provides a three-dimensional stacked fin metal oxide semiconductor (SF-MOS) device (10,30) comprising a protrusion or fin structure with a plurality of stacked semiconductor regions (3,5,12), in which a second semiconductor region (5,12) is separated from a first semiconductor region (3,5) by an isolation region (4,11). A gate isolation layer (8) extends at least over the sidewalls of the protrusion (7) and a gate electrode extends over the gate isolation layer (8). The gate electrode comprises a plurality of gate regions (13,14,15) wherein each gate region (13,14,15) extends over another semiconductor region (3,5,12). In this way each gate region (13,14,15) influences the conduction channel of another semiconductor region (3,5,12) and hence adds another degree of freedom with which the performance of the SF-MOS device (10,30) can be optimized. The invention further provides a method of manufacturing the SF-MOS device (10,30) according to the invention.
    Type: Grant
    Filed: January 22, 2007
    Date of Patent: January 10, 2012
    Assignee: NXP B.V.
    Inventor: Sebastien Nuttinck
  • Publication number: 20120001860
    Abstract: The present invention concerns a detection system and a corresponding method for detecting movements of a movable object that compensate for unintentional tilt movement of the movable object in a first direction and/or in a second direction when a linear movement in a third direction is detected.
    Type: Application
    Filed: June 21, 2011
    Publication date: January 5, 2012
    Applicant: NXP B.V.
    Inventor: Kim Phan Le
  • Publication number: 20120001570
    Abstract: A method is disclosed of controlling a LED, comprising driving the LED with a DC current for a first time, interrupting the DC current for a second time such that the first time and the second time sum to a period, determining at least one characteristic of the LED whilst the DC current is interrupted, and controlling the DC current during a subsequent period in dependence on the at least one characteristic. The invention thus benefits from the simplicity of DC operation. By operating at the LED in a DC mode, rather than say in a PWM mode, the requirement to be able to adjust the duty cycle is avoided. By including interruptions to the DC current, it is possible to utilise the LED itself to act as a sensor in order to determine a characteristic of the LED. The need for additional sensors is thereby avoided.
    Type: Application
    Filed: February 25, 2010
    Publication date: January 5, 2012
    Applicant: NXP B.V.
    Inventors: Peter Hubertus Franciscus Deurenberg, Gert-Jan Koolen, Gian Hoogzaad, Radu Surdeanu, Pascal Bancken, Benoit Bataillou, Viet Nguyen Hoang
  • Publication number: 20120001700
    Abstract: A method of manufacturing a MEMS resonator formed from a first material having a first Young's modulus and a first temperature coefficient of the first Young's modulus, and a second material having a second Young's modulus and a second temperature coefficient of the second Young's modulus, a sign of the second temperature coefficient being opposite to a sign of the first temperature coefficient at least within operating conditions of the resonator. The method includes the steps of forming the resonator from the first material; applying the second material to the resonator; and controlling the quantity of the second material applied to the resonator by the geometry of the resonator.
    Type: Application
    Filed: June 21, 2011
    Publication date: January 5, 2012
    Applicant: NXP B.V.
    Inventor: Robert J. P. Lander
  • Patent number: 8089302
    Abstract: The present application relates to an apparatus comprising a first transistor element, with at least three terminals, and at least one switching unit. The present application relates also to a method, computer readable medium having a computer program stored thereon and a track and hold circuit comprising the apparatus. The apparatus comprises a first transistor element with at least three terminals, wherein a first terminal is supplied with a first voltage, and wherein a second terminal is supplied with a second voltage. The apparatus comprises a first switching unit, wherein a third terminal is connected to ground potential via the first switching unit. The transistor element comprises a predefined threshold voltage. The first voltage and the second voltage are predefined alternating voltages.
    Type: Grant
    Filed: September 9, 2008
    Date of Patent: January 3, 2012
    Assignee: NXP B.V.
    Inventors: Simon Minze Louwsma, Maarten Vertregt
  • Patent number: 8089991
    Abstract: An embodiment of the invention includes a method and network for clock synchronization within a time triggered network using time slots, having at least two clusters. The clusters are connected to a coupling unit that includes a clock alignment control logic. The clock alignment control logic includes a coupling unit clock source which is more accurate than the node clock source. The accuracy of the coupling unit clock source is due to the coupling unit clock source including an oscillator crystal with smaller guaranteed deviations than the guaranteed deviations of the node clock source and/or the coupling unit clock source receiving a clock signal from an external clock device or from a GPS device. The method includes using a rate correction for offset correction.
    Type: Grant
    Filed: August 28, 2007
    Date of Patent: January 3, 2012
    Assignee: NXP B.V.
    Inventor: Joern Ungermann