Abstract: The invention relates to a memory controller for use in a System-on-Chip, wherein the System-on-Chip comprises a plurality of agents and an off-chip volatile memory. The memory controller comprises a first port (CBP) for receiving low-priority requests (CBR) for access to the volatile memory from a first-subset of the plurality of agents and a second port (LLP) for receiving high-priority requests (LLR) for access to the volatile memory from a second-subset of the plurality of agents, wherein the memory controller is configured for arbitrating between the high-priority requests (LLR) and the low-priority requests (CBR), wherein the memory controller is configured for receiving refresh requests (RFR) for the volatile memory via the first port (CBP), wherein the refresh requests (RFR) are time-multiplexed with the low-priority requests (CBR), wherein the memory controller is configured for treating the low-priority requests (CBR) and the refresh requests (RFR) the same.

Abstract: The estimated power levels that are used to estimate a signal-to-interference ratio (SIR) are filtered so as to minimize the mean-square error (MSE) of the estimated power estimates. First order infinite impulse response (IIR) filters are used to filter both the signal power estimates and the noise power estimates. Optionally, estimates of the average signal power and average interference power are filtered using Weiner linear prediction filters. The SIR estimates are suitable for use in a transmission channel that includes fading as well as interference, and are suitable for use in BPSK, QPSK, and other modulation systems.

Abstract: A shift register circuit is provided for storing instruction data for the testing of an integrated circuit core. The shift register circuit comprises a plurality of stages, each stage comprising a serial input (si) and a serial output (so) and a parallel output (wir_output) comprising one terminal of a parallel output of the shift register circuit. A first shift register storage element (32) is for storing a signal received from the serial input (si) and providing it to the serial output (so) in a scan chain mode of operation. A second parallel register storage element (38) is for storing a signal from the first shift register storage element (32) and providing it to the parallel output (wir_output) in an update mode of operation. The stage further comprises a feedback path (40) for providing an inverted version of the parallel output (wir_output) to the first shift register storage element (32) in a test mode of operation.

Abstract: The invention relates to a semiconductor device with a substrate and a semiconductor body of silicon comprising a bipolar transistor with an emitter region, a base region and a collector region which are respectively of the N-type conductivity, the P-type conductivity and the N-type conductivity by the provision of suitable doping atoms, wherein the base region comprises a mixed crystal of silicon and germanium, the base region is separated from the emitter region by an intermediate region of silicon having a doping concentration which is lower than the doping concentration of the emitter region and with a thickness smaller than the thickness of the emitter region, and the emitter region comprises a sub-region comprising a mixed crystal of silicon and germanium which is positioned at the side of emitter region remote from the intermediate region.

Abstract: Consistent with an example embodiment, an edge-rate control circuit arrangement (300) for an I2C bus application comprises a first circuit stage (10, M1, M3), responsive to a state transition of a received signal. A second circuit stage (310, 25, 20, 35, 45, M4, ESD) is responsive to the state transition of the received signal and includes drive circuitry (M4) that is activated in response to the state transition of the received signal in order to provide an edge-transition signal for an I2C bus, and regulation circuitry (310, R1, R2, M0, M2) adapted to control the drive circuit and regulate a transition rate for the edge-transition signal, the transition rate being greater than a transition rate of the received signal at the first circuit stage and greater than a minimum and less than a maximum transition rate designated for communication on the I2C bus.

Abstract: An electronic compass has a 2D magnetometer for determining two of the three components of the earth-magnetic field vector. Values for the magnitude and inclination of the field at the location of the device are given. If at least one of the body axes of the device is held horizontally in operational use, an educated guess can be made about the actual orientation of the device (e.g., heading and tilt angles) with respect to the earth. Accordingly, this compass is a very-low cost device.

Abstract: The present invention provides for an apparatus and method of controlling writing a signal to an optical disc in an optical disk system and including the step of generating a feedback signal to dynamically tune the signal output from a laser source, and including generating a plurality of timing signals serving to define a plurality of sampling windows for selecting data samples from RF signals derived from a signal reflected from the disc, generating a plurality of runlength selection signals to allow for measurement of light reflection at required runlength lands or pits, and measuring light reflected at a runlength land or pit in processing means and employing the measured signal as the said feedback signal for the said tuning of the signal source.

Abstract: An electronic device with an amplifier output stage (OS) and an over-current detection means (OCDM) for detecting an output over-current (IHS, ILS) of the output stage (OS) is provided. The over-current detection means (OCDM) comprises a level detection means (LDM) for detecting a level of the output current (IO) exceeding a first level of the output current (IDET), and a timing detection means (TDM) for detecting a duration during which the output current (IO) exceeds the first current level (IDET) being a maximum current level.

Abstract: In a circuit (2, 3) for processing at least one output signal (C1, C2, C3) of a communication stage, which at least one output signal (C1, C2, C3) of a communication stage can be generated by means of a communication stage, there are provided signal-mixing means (5), which signal-mixing means (5) are arranged to receive at least two output signals (C1, C2, C3) of communication stages and to mix the at least two output signals (C1, C2, C3) of communication stages and to transmit a collision signal representing the result of the mixing of the at least two output signals (C1, C2, C3) of communication stages, which collision signal represents a simultaneous occurrence of at least two output signals (C1, C2, C3) of communication stages in an electromagnetic field.

Abstract: Receiver for receiving a data stream via a data bus, which receiver samples the bits of the data stream in an over-sampling process, in which n bit strobe offsets are used and n data sets with i bits are sampled,—applies a decision criterion for identifying those data sets with correct bit values. This decision uses checksum CRC,—selects one of the identified data sets with correct bit values and—uses the bit strobe offset, which was used for receiving the selected data streams, for receiving the data stream. In this way the multiphase clock with optimal phase shifts is selected.

Abstract: Systems and methods are provided. In this regard, a representative system incorporates a crystal oscillator circuit and a digital automatic level control circuit. The digital automatic level control circuit is operative to: convert an oscillation amplitude of the crystal oscillator circuit to a proportional DC voltage; convert the DC voltage to a corresponding digital code representation; and adjust bias current and oscillator loop gain such that a desired oscillation amplitude is set.

Abstract: A bond wire circuit includes bond wires arranged relatively to provide a selected inductance. In connection with various example embodiments, respective bond wire loops including forward and return current paths are arranged orthogonally. Each loop includes a forward bond wire connecting an input terminal with an intermediate terminal, and a return bond wire connecting the intermediate terminal to an output terminal. The return bond wires generally mitigate return current flow from the intermediate terminal in an underlying substrate. In some implementations, the loops are arranged such that current flowing in each of the respective loops generates equal and self-cancelling current in the other of the respective loops.

Abstract: A method and apparatus for testing an integrated circuit core or circuitry external to an integrated circuit core using a testing circuit passes a test vector from a parallel input of the testing circuit along a shift register circuit. The shift register circuit is configured to bypass one or more cores not being tested and to provide the test vector to a core scan chain of the core being tested. The bypassed cores are configured such that the associated shift register circuit portion is driven to a hold mode in which storage elements of the shift register circuit portion have their outputs coupled to their inputs. This method provides holding of the shift register stages when a core is bypassed and in a test mode, and this means the shift register stages are less prone to errors resulting from changes in clock signals applied to the shift register stages.

Abstract: A method of manufacturing a bipolar transistor is compatible with FinFET processing. A collector region (18) is formed and patterned, base contact regions (26) formed on either side, and a gap formed between the base contact region. A base (28), spacers (30) and an emitter (32) are formed in the gap.

Abstract: Systems, devices and methods are implemented for compressing high-definition video content. Consistent with one such implementation, a device is implemented for preparing a media stream containing high-definition video content for transmission over a transmission channel. A receiver unit is arranged to receive the media stream in a high-definition encoding format that does not compress the high-definition video content contained therein. A decoder unit is arranged to decode the media stream. A compression unit is arranged to compress the decoded media stream to produce a compressed media stream. An encapsulation unit is arranged to encapsulate the compressed media stream within an uncompressed video content format. An encoding unit is arranged to encode the encapsulated media stream using the high-definition format to produce a data stream and may be arranged to encrypt the data stream, e.g., using High-Bandwidth Digital Content Protection (HDCP).

Abstract: An apparatus for restricting the thermo-mechanical stress in semiconductor wafers both during manufacture, and during the operating lifetime of the semiconductor devices and systems formed on the wafer. An electrically conductive track 8 can be formed with a stopper 16 which can be positioned at least at one end of the electrically conductive track 8. The differential expansion during heating of electrically conductive tracks 8 with respect to a semiconductor wafer 4 can be restricted by the stopper 16.

Abstract: The invention relates to a computer implemented method of interruption of meta language program code (10) execution on a computer having a micro controller (1) executing a native code (3) execution with a virtual machine (5) executing a meta language program code (10), where an address controller (15) controls the interruption of the meta language program code (10).

Abstract: Tasks are executed in a multiprocessing system with a master processor core (10) and a plurality of slave processor cores (12). The master processor core (10), executes a program that defines a matrix of tasks at respective positions in the matrix and a task dependency pattern applicable to a plurality of the tasks and defined relative to the positions. Each dependency pattern defines relative dependencies for a plurality of positions in the matrix, rather than using individual dependencies for individual positions. In response to the program the master processor core (10) dynamically stores definitions of current task dependency patterns in a dependency pattern memory. A hardware task scheduler computes the positions of the tasks that are ready for execution at run time from information from information about positions for which tasks have been completed and the task dependency pattern applied relative to those tasks.

Abstract: A low dropout (LDO) voltage regulator comprises a regulating element (10) having an input (12), an output (14) and a control terminal (16), an error amplifier (22) having a non-inverting input (28) coupled to a node (30) of a potential divider sampling an output voltage (Vo) at the output (14) of the regulating element, an inverting input (24) coupled to a source (26) of a reference voltage (Vref) and an output coupled to the control terminal (16) of the regulating element, and means for generating an internal zero. The means for generating an internal zero comprises an operational amplifier (52) having a non-inverting input (54) coupled to the node (30) of the potential divider, an output (58) coupled to the non-inverting input (28) of the error amplifier, a resistive element (60) connected between the output and an inverting input (56) of the operational amplifier and a capacitive element (62) coupled between the inverting input of the operational amplifier and the source of reference voltage.

Abstract: A system and method for obtaining an authorization key to use a product utilizes a secured product identification code, which includes a serial number and at least one code that is generated based on a cryptographic algorithm.