Abstract: Consistent with an example embodiment, there is a method for a method for processing video data, the video data being adapted for being displayed on a locally dimmable liquid crystal display. The method comprises color enhancing the video data. The method further comprises determining dimming factors corresponding to primary color components of the video data corresponding to a pixel of the locally dimmable liquid crystal display based on the color enhanced video data. The method furthermore comprises determining a color correction of the color enhanced video data corresponding to the pixel of the locally dimmable liquid crystal display based on the dimming factors. The method also comprises processing the video data based on the determined color correction.

Abstract: An electronic device is provided which comprises at least one processing unit (CPU) for processing at least one application having at least one task at least one operating frequency, an user event detecting unit (UED) for detecting at least one user event which initiates at least one task with an associated user event execution time, and a power manager (PM) for managing a power consumption of the processing unit (CPU) by controlling the operating frequency of the processing unit (CPU) in dependence of the associated user event execution time.

Abstract: A configurable fast Fourier transforms (FFT) apparatus to compute radix-2 and non-radix-2 calculations. The configurable FFT apparatus includes a data input, a data output, an interconnect, and a configuration manager. The data input retrieves an input data segment from a memory device. The data output stores processed data to the memory device. The interconnect routes radix FFT signals of multi-type radix configurations from the data input to the data output. The configuration manager dynamically configures the interconnect according to a determination of a current radix configuration.

Abstract: A switched capacitor pipeline ADC stage is disclosed, in which a reset switch is included to reset the sampling capacitor during a first part of the sampling period. The reset switch thereby removes history and makes the sampling essentially independent of previous samples taken, thus reducing inter symbol interference (ISI) and distortion resulting therefrom, without significantly affecting the sampling period or power usage of the device.

Abstract: A method of restoring a digital image, the method comprising partitioning the image into a plurality of blocks of pixels, processing each block to produce a restored block and concatenating the restored blocks to produce a restored digital image, wherein the step of processing each block comprises: i) padding the block with additional pixels having values extrapolated from a range of pixel values across the block to produce a padded block; si) performing a Fourier transform operation on the padded block to produce a transformed block; iii) applying an inverse blur filler to the transformed padded block to produce a filtered block; and Iv) performing an inverse Fourier transform on the filtered block to obtain the restored block.

Abstract: A frequency conversion circuit configured to mix a first input signal (RF+,RF?) at a first frequency with a second input signal (LO+,LO?) at a second frequency to provide an output intermediate frequency signal (IFout), the circuit comprising: first and second mixing modules , each mixing module comprising a voltage to current converter configured to receive the first input signal (RF+,RF?) and connected to a Gilbert mixer configured to receive the second input signal (LO+,LO?); an intermediate frequency output circuit having inputs connected to receive an intermediate frequency current signal (IF+,IF?) from outputs of each of the Gilbert mixers and an output configured to provide the output intermediate frequency voltage signal (IFout), wherein the first and second mixing modules comprise transistors which are complementary to each other.

Abstract: A circuit that comprises a processor core (100), a background memory (12) and a cache circuit (102) between the processor core (100) and the background memory (12). In operation a sub-range of a plurality of successive addresses is detected within a range of successive addresses associated with a cache line, the sub-range containing addresses for which updated data is available in the cache circuit. Updated data for the sub-range is selectively transmitted to the background memory (12). A single memory transaction for a series of successive addresses may be used, the detected sub-range being used to set the start address and a length or end address of the memory transaction. This may be applied for example when only updated data is available in the cache line, and no valid data for other addresses, or to reduce bandwidth use when only a small run of addresses has been updated in the cache line.

Abstract: A power supply includes a PFC stage 6 and an SMPS stage 8. The power supply can operate in a normal mode in which the PFC stage supplies a voltage to the SMPS stage. In a standby mode, the PFC stage is operated in bursts to supply a lower voltage to the SMPS stage that is high enough that the SMPS stage can rapidly respond when it needs to supply a load.

Abstract: A low-power high dynamic range RF input stage (200) with a noiseless degeneration component, such as a capacitor (201), is provided. High dynamic range means a combination of low noise contribution by the stage (200) and a low level of intermodulation products occurring especially at high input levels. Low power means that the power consumption of a conventional input stage is about 5 times higher than the power consumption of the stage according to the invention, for the same noise, gain and distortion level. This new stage can be used in amplifiers, but also in the lower stage of double balanced mixers (300-400) commonly used in RF receivers, examples of which are applications, are provided.

Abstract: A measuring method for measuring physical variables comprises the selection of a working point (AP) lying within a total measurement range (G) of a physical variable (M) to measured, the detection of a measured value (M(t1)) of the physical variable at a first measuring time (t1), the determination of a displacement value (V(t1)) as the result of a subtraction of the measures value (M(t1)) measured at the first measuring time from the working point (AP), the formation of change values (C(t2), C(t3) . . . C(tx)) of the physical variable (M) by acquiring subsequent measured values (M(t2), M(t3) . . . M(tx)) of the physical variable at subsequent measuring times (t2, t3 . . . tx) and addition of the displacement value (V(t1)) to the subsequent measured values.

Abstract: Consistent with one example embodiment, communications systems, using a serial data transfer bus having a serial data line and a clock line used to implement a communications protocol, incorporate programmable loading of a logic value into parallel slave device registers. The communications system includes a slave device having two or more registers, each register having two or more bits, each register configured to load data therein received in accordance with the communications protocol over the data transfer bus in a first configuration, and to load a single logic value into the plurality of bits in a second configuration. A programmable configuration register is configured to be programmed, in accordance with the communications protocol over the data transfer bus, to select two or more of the registers for loading of the single logic value into the two or more of bits of the selected registers in the second configuration.

Abstract: Consistent with an example embodiment, there is a signal processing circuit. Linking multiplexing (L-MUX) circuits, link respective pairs of stream processing circuits. Each L-MUX circuit is individually switchable to a normal mode and a replacement mode; in normal mode, it passes a first stream of samples values between the stream processing circuits in the respective pair of the L-MUX circuits; in replacement mode, it supplies successive sample values from a second stream from the communication structure to a receiving one of the stream processing circuits in the respective pair. A control circuit keeps a selectable one of the multiplexing circuits in the replacement mode so the selectable one of the L-MUX circuits passes a stream of successive samples from the second stream to the receiving one of the processing circuits in the respective pair of L-MUX circuits, while keeping at least part of the other L-MUX circuits in the normal mode.

Abstract: The invention relates to a semiconductor device (10) with a substrate (12) and a semiconductor body (11) of silicon comprising a bipolar transistor with an emitter region, a base region and a collector region (1,2,3) first conductivity type, a second conductivity type opposite to said first conductivity type and the first conductivity type, respectively, with a first semiconductor region (3) comprising the collector region or the emitter region being formed in the semiconductor body (11), on top of which a second semiconductor region (2) comprising the base region is present, on top of which a third semiconductor region (1) comprising the other of said collector region and said emitter region is present, said semiconductor body (11) being provided with a constriction at the location of the transition between the first and the second semiconductor region (3, 2), which constriction has been formed by means of an electrically insulating region (26, 27) buried in the semiconductor body (11).

Abstract: A power insulated gate field effect transistor has main cells (2) controlled by a main cell insulated gate and sense cells (4) controlled by a sense cell insulated gate. A sample and hold circuit (10, 50) is arranged to operate in a plurality of states including at least one sample state and a hold state to sense the current flowing through the sense cells (4) when in the at least one sample state but not in the hold state. The sample states may be used in a feedback loop to control a drive amplifier (20) driving the gates of the main and sense cells (2,4) and/or to mirror the current in the sense cells (4) on a measurement output terminal (58).

Abstract: A vibrating element (1) for an electroacoustic transducer, particularly for a loudspeaker, is provided, comprising a diaphragm (2) with at least two electrically conductive areas (3a, 3b) separated from each other, and with a recess (4). In the recess (4) a coil (5) is arranged with two connecting leads (6a, 6b), which are electrically contacted with one conductive area each (3a, 3b). The contact points (8a . . . 8d) are then located in the area of the recess (4). Furthermore, a method for the manufacturing of a vibrating element (1) is provided. The recess (4), the inserting of the coil (5) into the recess (4) as well as optionally the contacting of connecting leads (6a, 6b) with the conductive areas (3a, 3b) can then take place in one process step.

Abstract: A method of forming a substrate contact in a semiconductor device, comprising the steps of providing a semiconductor base substrate (2) having a buried oxide (BOX) layer (4) and a thin active semiconductor layer (103) on the BOX layer (4), forming a trench (104) in the active semiconductor layer (103) and the Box layer (4) to the semiconductor base substrate (2) below, and then depositing another active semiconductor (epitoxial) layer (6) over the remaining active semiconductor layer (103) and in the trench (104) to create the substrate contact. The trench (104) is etched at a location on the wafer corresponding to a scribe lane (106).

Abstract: A Dynamic Threshold Rule is provided for sharing of bandwidth of a shared medium between multiple devices. In one embodiment, a device determines a measure of available bandwidth of said medium; reserves bandwidth up to the available bandwidth; receives a request from a device for bandwidth of a specified amount; and honors the request when relinquishing the specified amount results in preserving an equal or greater percentage of bandwidth available at a time of reserving bandwidth. Different classes of devices may be distinguished, where the percentage for devices of a particular class is greater than for devices not of that particular class, or for which at least one class of device is exempt from the requirement to relinquish bandwidth.

Abstract: An instruction issue method for use in a pipelined processor, comprising the steps of: decoding an instruction to be processed to get a type of the instruction; computing the number of cycles to be occupied at execution stage for the instruction, according to the type of the instruction; marking a target operand of the instruction as acquirable in a predefined cycle before the instruction enters write-back stage, according to the number of cycles, so that subsequent instructions taking the target operand as their source operands perform subsequent operations according to the case that the target operand is acquirable.

Abstract: A finFET structure is made by forming a fin (14), followed by a gate stack of gate dielectric (16), metal gate layer (18), polysilicon layer (20) and silicon-germanium layer (22). The gate stack is then patterned, and source and drain implants formed in the fin (14) away from the gate. The silicon germanium layer (22) is selectively etched away, a metal deposited over the gate, and silicidation carried out to convert the full thickness of the polysilicon layer (20) at the top of the fin. A region of unreacted polysilicon (38) may be left at the base of the fin and across the substrate.

Abstract: A capacitive sensor amplifier circuit comprising: a capacitive sensor; a bias voltage supply connected across the capacitive sensor via a bias resistor; an operational amplifier having an input connected to the capacitive sensor; and a feedback capacitor connected between the input and an output of the amplifier, the input and output being of the same sign.