Abstract: The present invention discloses a method of forming a local buried layer (32) in a silicon substrate (10), comprising forming a plurality of trenches (12, 22) in the substrate, including a first trench (22) having a width preventing sealing of the first trench in a silicon migration anneal step and at least one further trench (12) connected to the first trench; exposing the substrate (10) to said anneal step, thereby converting the at least one further trench (12) by means of silicon migration into at least one tunnel (16) accessible via the first trench (22); and forming the local buried layer (32) by filling the at least one tunnel (16) with a material (26, 28, 46) via the first trench (22). Preferably, the method is used to form a semiconductor device having a local buried layer (32) comprising a doped epitaxial silicon plug (26), said plug and the first trench (22) being filled with a material (28) having a higher conductivity than the doped epitaxial silicon (26).

Abstract: A method of determining the ageing characteristics of an LED comprises applying a current stress pulse to the LED. The LED is monitored to determine when the thermal heating induced by the current stress pulse has been dissipated to a desired level. The operational characteristics of the LED are then measured before applying the next stressing pulse. This method accelerates the effect of aging in a reproducible way and therefore is able to greatly reduce the time needed for a reliability test.

Abstract: A data processing system, a turbo decoding system, an address generator and a method of reconfiguring a turbo decoding method is provided. The data processing system (101) comprises the turbo decoding system (100). The turbo decoding system (100) comprises electronic circuits. The electronic circuits comprises: a memory (108), the address generator (102), and a Soft Input Soft Output decoder (106). The address generator (102) is operative to produce a sequence of addresses according to an interleaving scheme. The address generator can support multiple interleaving schemes. The address generator (102) is operative to receive reconfiguration information. The address generator (102) is operative to reconfigure during operational use the interleaving scheme in dependency on the reconfiguration information.

Abstract: The invention relates to a semiconductor device includes a substrate (1000; 2000), a solar cell (1910; 2910) formed on the substrate (1000; 2000) and a battery (1900; 2900) formed on the substrate, the battery comprising a plurality of trench batteries in a plurality of corresponding trenches (1400; 2400) in the substrate (1000; 2000). The solar cell can include a silicon solar cell (1910) comprising a plurality of p-n junctions for, during use, receiving incident light and converting at least part of the received incident light into an electrical current. Alternatively, the solar cell can include an electrochemical cell (2910) for, during use, receiving incident light and converting at least part of the received incident light into an electrical current. The invention further relates to a manufacturing method for a semiconductor device. The invention further relates to an apparatus comprising a semiconductor device.

Abstract: In order to further develop a method of and a system (100) for controlling the programming of, in particular the erase/write access to, a memory device (10) comprising multiple memory cells (20, 22), said memory cells (20, 22) being exposed to wear resulting from repeated programming, in such way that an increased lifetime of the memory device (10), in particular on an integrated circuit, is provided even under exceptional stress of the memory device (10), it is proposed to provide—at least one quality measuring/determining means (40, 42) being assigned to each memory cell (20, 22) in order to measure and/or to determine the quality of the respective memory cell (20, 22), in particular in order to measure and/or to determine the prospective endurance specified according to a number of change cycles which the respective memory cell (20, 22) can endure within a performance tolerance, and—at least one control means (50), in particular by at least one access load distributor, —being coupled to each quality measur

Abstract: The present invention relates to a gigitaol phaselocked loop DPLL (300, 400) having a phase-to-digital P2D (60) with an enhanced bang-bang phase detector BBPD. Such a P2D (60) comprises a BBPD (62), an additional digital circuit (200) including a sign detector (210), a counter (220) and a mapping function (230), and a summer block (64). During the locking process, the BBPD (62) may-output a repeating value, namely a string of data bits of same polarity value either “+1” or “?1”. The polarity sign is detected by the sign detector (210), and the data string length is determined by the counter (220) that is reset to zero whenever the BBPD output changes sign. The mapping function (230) is configured for mapping the data string length in input to the phase correction level in output Its output is added to that of the BBPD (62) through the summer block (64), such that the phase correction level is increased to enhance the locking process whenever a data string is detected.

Abstract: Method of manufacturing a non-volatile memory device on a semiconductor substrate in a memory area, said non-volatile memory device comprising a cell stack of a first semiconductor layer, a charge trapping layer and an electrically conductive layer, the charge trapping layer being the intermediate layer between the first semiconductor layer and the electrically conductive layer, the charge trapping layer comprising at least a first insulating layer; the method comprising: —providing the substrate having the first semiconductor layer; —depositing the charge trapping layer; —depositing the electrically conductive layer; —patterning the cell stack to form at least two non-volatile memory cells, and —creating a shallow trench isolation in between said at least two non-volatile memory cells.

Abstract: An apparatus and corresponding method are disclosed that uses one or more optical fibers in a susceptor that monitor radiation emitted by the backside of the susceptor. The optical fibers are filtered and converted into an electrical signal. A control system is used to maintain a constant wafer temperature by keeping the electrical signal constant during the deposition cycle. This overcomes problems caused by varying wafer temperature during non-selective epitaxial and poly-silicon growth on patterned wafers at low temperatures and reduced pressure.

Abstract: An analogue to digital conversion unit (208, 210) comprises three analogue to digital converters (ADCs) (300, 301, 302) having different dynamic ranges. A lowest dynamic range ADC (300) and middle dynamic range ADC (301) have saturation detectors SAT for outputting a signal when the amplitude of an input analogue signal reaches their respective dynamic ranges and saturates them. The middle dynamic range ADC (301) and highest dynamic range ADC have enable inputs EN for switching themselves on. The output of the saturation detector SAT of the lowest dynamic range ADC (300) is connected to the enable input EN of the middle dynamic range ADC (301). The output of the saturation detector SAT of the middle dynamic range ADC (301) is connected to the enable input EN of the highest dynamic range ADC (302).

Abstract: The invention relates to the manufacture of an epitaxial layer, with the following steps: providing a semiconductor substrate; providing a Si—Ge layer on the semiconductor substrate, having a first depth; —providing the semiconductor substrate with a doped layer with an n-type dopant material and having a second depth substantially greater than said first depth; performing an oxidation step to form a silicon dioxide layer such that Ge atoms and n-type atoms are pushed into the semiconductor substrate by the silicon dioxide layer at the silicon dioxide/silicon interface, wherein the n-type atoms are pushed deeper into the semiconductor substrate than the Ge atoms, resulting in a top layer with a reduced concentration of n-type atoms; removing the silicon dioxide layer; growing an epitaxial layer of silicon on the semiconductor substrate with a reduced outdiffusion or autodoping.

Abstract: A Modification device (5) is designed to modify an application (A1, A2, A3, A4) run by a data carrier (S), wherein a first key information item (K1) is stored in the data carrier (S) and an associated second key information item (K2) is stored in the modification device.

Abstract: There is a process for reducing the sheet resistance of phosphorus-implanted poly-silicon. In an example embodiment, there is an MOS transistor structure. The structure has a gate region, drain region and a source region. A method for reducing the sheet resistance of the gate region comprises depositing intrinsic amorphous silicon at a predetermined temperature onto the gate region. An amorphizing species is implanted into the intrinsic amorphous silicon. Phosphorus species are then implanted into the gate region of the MOS transistor structure. A feature of this embodiment includes using Ar+ as the amorphizing species.

Abstract: The present invention relates to a method for fabricating a planar independent-double-gate FET or a planar gate-all-around FET on a bulk semiconductor substrate. The method comprises refilling a surface recess in an active semiconductor region with a buried sacrificial layer, and, after preparing a pre-processing a gate stack by respective deposition and patterning, the formation of a recess in the isolation regions so as to cause the recess to extend, in a depth direction that points towards the inner substrate, to a depth level that allows removing the buried sacrificial layer and so as to cause the recess to undercut portions of gate stack in the channel direction.

Abstract: A method of manufacturing a semiconductor device wherein a laminate structure comprising a sacrificial layer is sandwiched between two etch stop layers (8,11) and which separates a semiconductor membrane (9) from a bulk substrate (1) is used to provide an underetched structure. Access trenches (4) and support trenches (5) are formed in the layered structure through the thickness of the semiconductor layer (9) and through the upper etch stop layer (8). The support trenches extend deeper through the sacrificial layer (12) and the lower etch stop layer and are filled. The sacrificial layer is exposed and etched away selectively to the etch stop layers to form a cavity (30) and realise a semiconductor membrane which is attached to the bulk substrate via a vertical support structure comprising the filled support trenches.

Abstract: A One Time Programmable (OTP) memory cell (10) comprising a first, metallic layer (12) coated with a second, conductive stable transition compound (14) with an insulating layer (16) there-between. The first and second layers (12, 14) are selected according to the difference in Gibbs Free Energy between them, which dictates the chemical energy that will be generated as a result of an exothermic chemical reaction between the two materials. The materials of the first and second layers (12, 14) are highly thermally stable in themselves but, when a voltage is applied to the cell (10), a localized breakdown of the insulative layer (16) results which creates a hotspot (18) that sets off an exothermic chemical reaction between the first and second layers (12, 14). The exothermic reaction generates sufficient heat (20) to create a short circuit across the cell and therefore reduce the resistance thereof.

Abstract: A method of making a FET includes forming a gate structure (18), then etching cavities on either side. A SiGe layer (22) is then deposited on the substrate (10) in the cavities, followed by an Si layer (24). A selective etch is then carried out to etch away the SiGe (22) except for a part of the layer under the gate structure (18), and oxide (28) is grown to fill the resulting gap. SiGe source and drains are then deposited in the cavities. The oxide (28) can reduce junction leakage current.

Abstract: A resonator having an effective spring constant (kz) and comprising a beam having a beam spring constant (kB) adapted to resonate in an oscillation direction, and extending at a non-zero angle (?) to the oscillation direction, wherein the resonator has a predetermined geometry and is formed from one or more materials, the or each material having a coefficient of thermal expansion (CTE), the CTE of the or each material together with the predetermined geometry of the resonator causing ? to vary with temperature, such that the temperature dependence of the beam spring constant is compensated for, resulting in the effective spring constant of the resonator remaining substantially constant within an operating temperature range.

Abstract: A method of estimating the output light flux of a light emitting diode, comprises applying a drive current waveform to the LED over a period of time comprising a testing period. The forward voltage across the LED is monitored during the testing period, and the output light flux is estimated as a function of changes in the forward voltage.

Abstract: Data is processed using a first and second processing circuit (12) coupled to a background memory (10) via a first and second cache circuit (14, 14?) respectively. Each cache circuit (14, 14?) stores cache lines, state information defining states of the stored cache lines, and flag information for respective addressable locations within at least one stored cache line. The cache control circuit of the first cache circuit (14) is configured to selectively set the flag information for part of the addressable locations within the at least one stored cache line to a valid state when the first processing circuit (12) writes data to said part of the locations, without prior loading of the at least one stored cache line from the background memory (10). Data is copied from the at least one cache line into the second cache circuit (14?) from the first cache circuit (14) in combination with the flag information for the locations within the at least one cache line.

Abstract: A sensor comprising a silicon substrate having a first and a second surface, integrated circuitry provided on the first surface of the silicon substrate, and a sensor structure provided on the second surface of the silicon substrate. The sensor structure and the integrated circuitry are electrically coupled to each other.