Abstract: A chip integrated ion sensor is provided, which comprises a substrate having arranged thereon an electrolyte insulator semiconductor structure and a reference electrode. In particular, the electrolyte insulator semiconductor (EIS) structure may be formed on a chip already processed, i.e. the EIS structure may be formed in a Back End process on an already formed chip comprising a plurality of formed electronic components. In particular, the ion sensor may be adapted to form an ion concentration sensor, e.g. a pH sensor, i.e. may form a pH sensor. The reference electrode may be a non-polarizable electrode. In particular, the reference electrode may comprise Ag or AgCl as material.

Abstract: Tasks are executed in a multiprocessing system with a master processor core (10) and a plurality of slave processor cores (12). The master processor core (10), executes a program that defines a matrix of tasks at respective positions in the matrix and a task dependency pattern applicable to a plurality of the tasks and defined relative to the positions. Each dependency pattern defines relative dependencies for a plurality of positions in the matrix, rather than using individual dependencies for individual positions. In response to the program the master processor core (10) dynamically stores definitions of current task dependency patterns in a dependency pattern memory. A hardware task scheduler computes the positions of the tasks that are ready for execution at run time from information from information about positions for which tasks have been completed and the task dependency pattern applied relative to those tasks.

Abstract: Systems, devices and methods are implemented for compressing high-definition video content. Consistent with one such implementation, a device is implemented for preparing a media stream containing high-definition video content for transmission over a transmission channel. A receiver unit is arranged to receive the media stream in a high-definition encoding format that does not compress the high-definition video content contained therein. A decoder unit is arranged to decode the media stream. A compression unit is arranged to compress the decoded media stream to produce a compressed media stream. An encapsulation unit is arranged to encapsulate the compressed media stream within an uncompressed video content format. An encoding unit is arranged to encode the encapsulated media stream using the high-definition format to produce a data stream and may be arranged to encrypt the data stream, e.g., using High-Bandwidth Digital Content Protection (HDCP).

Abstract: A low dropout (LDO) voltage regulator comprises a regulating element (10) having an input (12), an output (14) and a control terminal (16), an error amplifier (22) having a non-inverting input (28) coupled to a node (30) of a potential divider sampling an output voltage (Vo) at the output (14) of the regulating element, an inverting input (24) coupled to a source (26) of a reference voltage (Vref) and an output coupled to the control terminal (16) of the regulating element, and means for generating an internal zero. The means for generating an internal zero comprises an operational amplifier (52) having a non-inverting input (54) coupled to the node (30) of the potential divider, an output (58) coupled to the non-inverting input (28) of the error amplifier, a resistive element (60) connected between the output and an inverting input (56) of the operational amplifier and a capacitive element (62) coupled between the inverting input of the operational amplifier and the source of reference voltage.

Abstract: A voltage regulator includes an active control switch, an active sync switch, a driver circuit, and a gate resistor. The active control switch is coupled between an input voltage line and an input of an energy storage device. The active sync switch is coupled to the input of the energy storage device. The driver circuit is coupled to the control and sync switches to alternately drive each of the control and sync switches into a conducting state to produce a regulated voltage at an output of the energy storage device. The gate resistor is coupled in series within a control path of the sync switch. The gate resistor has a resistance value that is tuned to reduce an anticipated dead time between a turn-off time of the sync switch and a turn-on time of the control switch.

Abstract: The present invention relates to a luminescent component (30) and a manufacturing method thereof. The luminescent component (30) comprises a first transparent carrier (18), a second transparent carrier (24), a substrate (10) sandwiched between said transparent carriers (18; 24), the substrate (10) comprising a conduit from the first transparent layer (18) to the second transparent carrier (24), the conduit being filled with a luminescent solution (20). This facilitates the use of colloidal solutions of quantum dots in such a luminescent component (30). Preferably, the substrate (10) is direct bonded to the transparent carriers (18, 24) using direct wafer bonding techniques.

Abstract: A device (100) for processing an input signal (102), the device (100) comprising a delay unit (104) adapted for delaying the input signal (102) by a predefined delay time, at least one phase shifting unit (106) each adapted for phase shifting the delayed input signal (108) by an assigned phase value, a plurality of mixer units (110) each adapted for mixing the input signal (102) with the delayed input signal (108) or with one of the at least one phase shifted signal (112), and an extraction unit (114) adapted for extracting information from each of the mixed signals (116).

Abstract: A data processing system is provided which comprises at least two processing units (100, 101, 102) each for executing a plurality of tasks and an interrupt handling unit (200) for receiving an interrupt to be processed by the data processing system and for distributing the interrupt to one of the at least two processing units (100, 101, 102). The processing unit (100, 101, 102) to which the interrupt is distributed stops its current execution of the task and processes the interrupt. The interrupt handling unit (200) is adapted to determine whether the processing units (100, 101, 102) are executing a critical section (CS) of the task. The interrupt handling unit (200) distributes the interrupt to one of the processing units (100, 101, 102), which is not executing a critical section (CS) of a task.

Abstract: The invention relates to a computer implemented method of interruption of meta language program code (10) execution on a computer having a micro controller (1) executing a native code (3) execution with a virtual machine (5) executing a meta language program code (10), where an address controller (15) controls the interruption of the meta language program code (10).

Abstract: A method of operating a micro-electromechanical system, comprising a resonator; an actuation electrode; and a first detection electrode, to filter and mix a plurality of signals. The method comprises applying a first alternating voltage signal to the actuation electrode, wherein an actuation force is generated having a frequency bandwidth that is greater than and includes a resonant bandwidth of a mechanical frequency response of the resonator, and wherein a displacement of the resonator is produced which is filtered by the mechanical frequency response and varies a value of an electrical characteristic of the first detection electrode. The method also comprises applying a second alternating voltage signal to the first detection electrode, wherein the second voltage signal is mixed with the varying value to produce a first alternating current signal. The first alternating current signal is detected at the first detection electrode.

Abstract: A wireless media arrangement streams media over a local packet-based wireless network. According to an example embodiment, such a wireless media arrangement (e.g., 100) includes a digitally-encoded non-volatile storage device (NSD) (e.g., 110) such as a hard disc drive (HDD) that stores media, reloadable memory (e.g., 115) such as random-access memory (RAM), a media center (e.g. 105) to stream the stored media to a media playback device over the local network, and an embedded media server (e.g., 120). The media server wirelessly discovers and communicates with a media playback device (e.g., 125) on a local network. The media server also stores database tables on the NSD identifying the stored media. Upon startup, the media server loads a current version of the database tables into the reloadable memory; however, if an error is detected in the current version, then a pervious version of the database tables is loaded.

Abstract: The memory circuit comprises at least one memory element (T1), a sense amplifier (SA) for sensing a state of the memory element (T1), a switching device (T2) for selectively coupling the sense amplifier (SA) to the memory element (T1), The sense amplifier (SA) comprises a first module (M1) and a second module (M2). The first module (M1) provides a first current limited to a maximum value (Iref+Ibias). The second module (M2) provides a second current which decreases from a value higher than the maximum value at the start of a sensing operation until a value lower than the maximum value at the end of the sensing operation. The memory circuit has a third module (CS2) for sinking a third current (Ibias) at a side of the switching device (T2) coupled to the memory element (T1).

Abstract: A method of visualizing a large still picture on a display having a size smaller than the large still picture includes the steps of dividing the large still picture into a set of pieces, where the pieces have a size substantially equal to the display size; ranking the pieces of the large still picture according to a predetermined scanning order; and encoding the set of pieces using a predictive block-based compression technique according to the predetermined scanning order so as to obtain a video sequence.

Abstract: A sample-and-hold feed switch has parallel PMOS branches and parallel NMOS branches, each extending from an input node to an output node connected to a hold capacitor. Each PMOS branch has a PMOS switch FET connected to a matching PMOS dummy FET, and each NMOS branch has an NMOS switch FET connected to a matching NMOS dummy FET. A sample clock switches the PMOS switch FETs on and off, and a synchronous inverse sample clock effects complementary on-off switching of the PMOS dummy FETs. Concurrently, a synchronous inverse sample clock switches the NMOS switch FETs on and off, and the sample clock effects a complementary on-off switching of the NMOS dummy FETs. A bias sequencer circuit biases the bodies of the PMOS switch FETs and the bodies of the PMOS dummy FETs, in a complementary manner, and biases the NMOS switch FETs and the NMOS dummy FETs, also in a complementary manner.

Abstract: The present invention relates to an integrated-circuit device and to a method for fabricating an integrated-circuit device with an integrated fluidic-cooling channel. The method comprises forming recesses in a dielectric layer sequence at desired lateral positions of electrical interconnect segments and at desired lateral positions of fluidic-cooling channel segments. A metal filling is deposited in the recesses of the dielectric layer sequence so as to form the electrical interconnect segments and to form a sacrificial filling in the fluidic-cooling channel segments. Afterwards, the sacrificial metal filling is selectively removed from the fluidic-cooling channel segments.

Abstract: The invention relates to multi-phase clock system for receiving a plurality of clock signals (CLKo-n) comprising actual time events (aTE) defining different clock phases, the clock signals all having a same clock frequency but different clock phases, the system further arranged for receiving a reference clock signal (REFCLK) for providing reference time events (rTE) for the plurality of clock signals (CLKo-n), the reference clock signal (REFCLK) having a reference frequency different from the clock frequency, the reference frequency being selected such that each one of the subsequent reference time events (rTE) coincides with a desired time event (dTE) for a single one of the plurality of clock signals (CLKo-n).

Abstract: The invention relates to an integrated circuit having a system base chip of the kind usually provided for performing transmitting and/or receiving functions at a node that is coupled to a vehicle data bus. In an example embodiment, there is an integrated circuit having a system base chip that has basic functions for a transmitting and/or receiving system for a vehicle data bus, namely at least a system voltage supply, a system reset and a monitoring function An interface circuit that, in a self-contained fashion, runs at least parts of a data bus protocol, and in particular, the LIN (Local Interconnect Network) protocol, that performs detection of the bit-rate of received data, and that is capable of passing on at least one received or transmitted byte. A serial/parallel converter makes use in its conversion of the bit-rate detected by the interface circuit.

Abstract: A power controller (10) includes a controller (11) and a trigger circuit (12). When the voltage of a power supply received at terminals T1 exceeds a threshold, for example 120 V RMS, reverse-connected Zener diodes Z1 to Z3 conduct and switch on a transistor Q1. This results in a transistor Q2 being switched off and a normally open relay SW1 remaining open. The switching or triggering phase angle of a triac THY1 thus is determined by the speed at which a capacitor C4 is charged to a triggering voltage by current flowing through resistors R6, R7, R8 and VR1. In this situation, the triggering phase angle is such that a 240 V AC input supply provides an effective 110 V AC output at terminals T3 when VR1 is at maximum power setting (zero Ohms). When the voltage of the received power supply is less than the threshold, the transistor Q1 is switched off and the relay SW1 is activated.

Abstract: A switched capacitor pipeline ADC stage is disclosed, in which a reset switch is included to reset the sampling capacitor during a first part of the sampling period. The reset switch thereby removes history and makes the sampling essentially independent of previous samples taken, thus reducing inter symbol interference (ISI) and distortion resulting therefrom, without significantly affecting the sampling period or power usage of the device.

Abstract: A low-power high dynamic range RF input stage (200) with a noiseless degeneration component, such as a capacitor (201), is provided. High dynamic range means a combination of low noise contribution by the stage (200) and a low level of intermodulation products occurring especially at high input levels. Low power means that the power consumption of a conventional input stage is about 5 times higher than the power consumption of the stage according to the invention, for the same noise, gain and distortion level. This new stage can be used in amplifiers, but also in the lower stage of double balanced mixers (300-400) commonly used in RF receivers, examples of which are applications, are provided.