Abstract: During a sampling phase, an analog front end circuit connects input of a first sampling capacitor to an analog input signal and input of a second sampling capacitor to a reference signal, and connects first and second hold capacitors to ground. During a partial tracking phase, input of the first sampling capacitor is connected to the reference voltage and the input of the second sampling capacitor is connected to the analog input signal. The first hold capacitor is connected to a first output of a gain amplifier and the second hold capacitor to a second output of the gain amplifier. Output of the first sampling capacitor is coupled to a first input of an amplifier and output of the second sampling capacitor is coupled to a second input of the amplifier.

Abstract: Embodiments of a method, an IC device, and a circuit board are disclosed. In an embodiment, the method involves at an IC device of the system, monitoring activity on a bus interface of the IC device, wherein the bus interface is connected to a bus on the system that communicatively couples the IC device to at least one other IC device on the system, applying machine learning to data corresponding to the monitored activity to generate an activity profile, monitoring subsequent activity on the bus interface of the IC device, comparing data corresponding to the to subsequently monitored activity to the machine learning generated activity profile to determine if a system-level Trojan is detected, and generating a notification when it is determined from the comparison that a system-level Trojan has been detected.

Abstract: A method and data processing system for detecting tampering of a machine learning model is provided. The method includes training a machine learning model. During a training operating period, a plurality of input values is provided to the machine learning model. In response to a predetermined invalid input value, the machine learning model is trained that a predetermined output value will be expected. The model is verified that it has not been tampered with by inputting the predetermined invalid input value during an inference operating period. If the expected output value is provided by the machine learning model in response to the predetermined input value, then the machine learning model has not been tampered with. If the expected output value is not provided, then the machine learning model has been tampered with. The method may be implemented using the data processing system.

Abstract: A method is provided for detecting copying of a machine learning model. In the method, the first machine learning model is divided into a plurality of portions. Intermediate outputs from a hidden layer of a selected one of the plurality of portions is compared to corresponding outputs from a second machine learning model to detect the copying. Alternately, a first seal may be generated using the plurality of inputs and the intermediate outputs from nodes of the selected portion. A second seal from a suspected copy that has been generated the same way is compared to the first seal to detect the copying. If the first and second seals are the same, then there is a high likelihood that the suspected copy is an actual copy. By using the method, only the intermediate outputs of the machine learning model outputs have to be disclosed to others, thus protecting the confidentiality of the model.

Abstract: Embodiments described herein include radio frequency (RF) switches that may provide increased power handling capability. In general, the embodiments described herein can provide this increased power handling by equalizing the voltages across transistors when the RF switch is open. Specifically, the embodiments described herein can be implemented to equalize the source-drain voltages across each field effect transistor (FET) in a FET stack that occurs when the RF switch is open and not conducting current. This equalization can be provided by using one or more compensation circuits to couple one or more gates and transistor bodies in the FET stack in a way that at least partially compensates for the effects of parasitic leakage currents in the FET stack.

Abstract: A near-field communication (NFC) receiver includes first and second input terminals for receiving first and second input signals having a modulated signal portion and a carrier signal portion. The receiver includes a digital-to-analog converter (DAC), a mixer, a track-and-hold (T&H) circuit, an amplifier, and an analog-to-digital converter. The mixer has a first input coupled to receive the first and second input signals and a second input coupled to receive a low frequency current from the DAC. The mixer subtracts the carrier portion from the first and second input signals using the DAC current at a level determined using a DSP in a feedback loop to approximate the carrier. The T&H circuit has an input coupled to receive the combined current and an output to provide a series of output samples. The ADC is coupled to receive the amplified output signal and to provide a digital representation of the amplified output signal.

Abstract: The disclosure relates to a controller and a transceiver and associated software and methods.

Abstract: An image processing system for convolving an image includes processing circuitry that is configured to retrieve the image including a set of rows, a merged kernel, multiple skip values and a pixel base address. The merged kernel includes all non-zero coefficients of a set of kernels. Each skip value corresponds to a location offset of each non-zero coefficient with respect to a previous non-zero coefficient. Further, the processing circuitry is configured to execute a multiply-accumulate (MAC) instruction and a load instruction parallelly in one clock cycle for multiple times, on the set of rows and the merged kernel to convolve the image with the merged kernel. Each row on which the MAC and load instructions are executed is associated with a corresponding non-zero coefficient and a corresponding skip value. The load instruction is executed based on the pixel base address, the corresponding skip value, and a width of each row.

Abstract: The disclosure relates to a controller area network, CAN, unit and associated method and computer program. The CAN unit is configured to detect a transmit signal edge on a transmit signal for a CAN transceiver; detect a corresponding receive signal edge on a receive signal for a CAN controller of the CAN transceiver; and detect a collision on the CAN bus based on a propagation delay between the transmit signal edge and the corresponding receive signal edge.

Abstract: An amplifier module includes a module substrate and first and second power transistor dies. The first power transistor die is coupled to a mounting surface of the module substrate, and has first and second input/output (I/O) contact pads and a first ground contact pad, all of which are all exposed at a surface of the first power transistor die that faces toward the mounting surface of the module substrate. The second power transistor die also is coupled to the mounting surface, and has third and fourth I/O contact pads and a second ground contact pad. The third and fourth I/O contact pads are exposed at a surface of the second power transistor die that faces away from the mounting surface of the module substrate, and the second ground contact pad is exposed at a surface of the second power transistor die that faces toward the mounting surface.

Abstract: The disclosure relates to a system and method for maintaining stability during a scan shift operation on multiple embedded memories in an integrated circuit. Examples disclosed herein include an integrated circuit comprising a plurality of memory modules and a built-in self-test controller, wherein the BIST controller and memory modules are arranged and configured to reduce toggling of cells in the memory modules during a scan shift operation.

Abstract: A Controller Area Network (CAN) transceiver includes a receiver configured to determine a voltage differential signal from analog signalling received from a CAN bus and configured to provide a digital output signal at a receiver output to a CAN controller based on the voltage differential signal. The receiver includes arming circuitry configured to place the receiver in an armed or unarmed state based on the voltage differential signal, a first threshold corresponding to a first CAN protocol, and a second threshold corresponding to a second CAN protocol. When the receiver is in the unarmed state, a first digital signal indicative of activity on the CAN bus is provided based on a comparison between the voltage differential signal and the first threshold, and when in the armed state, the first digital signal is provided based on comparisons between the voltage differential signal and each of the first and the second thresholds.

Abstract: An integrated circuit includes a primary initiator domain (ID) circuit including having a processor core, a responder domain (RD) control circuit, and a reset controller. Secondary ID circuits, each include a processor core and a reset controller. RD circuitry is coupled to communicate with the primary ID circuit and the secondary ID circuits and includes RD resource circuits. The RD control circuit is configured to allocate each of the RD resource circuits to a first initiator domain consisting of the primary ID circuit or one of the secondary ID circuits, and when one of the secondary ID circuits enters a reset mode of operation, the RD resource circuit allocated to the one of the secondary ID circuits enters a reset while the remaining RD resource circuits are not affected by the reset.

Abstract: A clock generator includes an input coupled to receive an input clock signal from a first clock source, and a noise rejection circuit configured to provide an output clock signal based on the input clock signal. The noise rejection circuit includes an event generator having a digital counter circuit. The event generator is configured to generate a first event signal based on a count value of the digital counter circuit, in which the noise rejection circuit is configured to produce an edge on the output clock signal in response to both the event signal and a state of the input clock signal.

Abstract: In accordance with a first aspect of the present disclosure, a radio frequency identification (RFID) transponder is provided, comprising a charge pump and at least one functional component, wherein: the charge pump is configured to convert an input voltage into an output voltage and to supply the output voltage to the functional component; the functional component is configured to perform a function of the RFID transponder using the output voltage of the charge pump; wherein the charge pump comprises a diode or switch transistor and at least one capacitor coupled to said diode or switch transistor, and wherein the capacitor is configured to compensate for a change of an impedance of said diode or switch transistor. In accordance with a second aspect of the present disclosure, a corresponding method of operating an RFID transponder is conceived.

Abstract: One example discloses a switched mode power supply device, comprising: an energy storage device; a controller configured to discharge the energy storage device; a voltage drop device having a first pin coupled to the energy storage device, a second pin coupled to the controller, and a third pin coupled to receive a first power-down signal; wherein the first power-down signal indicates that the energy storage device is to be discharged; wherein the voltage drop device is configured to input a first voltage from the energy storage device on the first pin and output a second voltage to the controller on the second pin; and wherein the second voltage is lower than the first voltage.

Abstract: In accordance with a first aspect of the present disclosure, a channel equalizer is provided for use in a near field communication (NFC) device, the channel equalizer comprising: a filter configured to receive an input signal and to generate a filtered output signal; an estimator configured to determine filter coefficients to be used by said filter; a synchronizer configured to determine when to enable the channel equalizer and to provide one or more corresponding control signals to the estimator. In accordance with a second aspect of the present disclosure, a corresponding method of operating a channel equalizer for use in a near field communication (NFC) device is conceived.

Abstract: An example apparatus includes a circuit and calibration circuitry. The circuit has complementary input ports to receive input signals including a monotonously rising and/or falling wave reference signal and a voltage-test signal to test at least one direct current (DC) voltage associated with the circuit by comparing the input signals using a first polarity and second polarity associated with the circuit to produce a first output signal and a second output signal. During operation, the circuit manifests an input voltage offset and a signal delay with each comparison of the input signals. The calibration circuitry processes the first and second output signals and, in response, calibrates or sets an adjustment for at least one signal path associated with the circuit in order to account for the input offset voltage and signal delay during normal operation of the circuit.

Abstract: In an 802.11az wireless system, a first station device transmits an NDP PPDU data unit in accordance with a range measurement packet exchange by constructing the NDP PPDU data unit to include an uplink (UL) length field element or a legacy signal length (LLEN) field element derived from a specified number of symbols (NHE-LTF) and number of repetitions (NLTF-REP) for the NDP PPDU data unit, and then sending the NDP PPDU data unit to a second STA device, where the values of the UL-length and LLEN field elements are computed as UL-Length=LLEN=10+y+6*?i=1NUM_USERS((NLTF-REP(i)+1)*NHE-LTF(i)), where y=0 for NTB I2R/R2I NDP and TB R2I NDP PPDUs, and where y=3 for TB-I2R NDP PPDUs.

Abstract: A dynamic safe state control circuit is disclosed that controls an electrical motor based on vehicle speed. A microcontroller or other processing device is configured to control an inverter system of an electrical motor. The dynamic safe state control circuit is configured to receive a first signal that corresponds to a speed of the electric motor. The circuit is configured to activate any one of a plurality of safe states in the inverter system based on the first signal and in response to a malfunction in the microcontroller.