Abstract: A level shifter includes a control circuit and a bias circuit. The control circuit receives a bias voltage, a first signal associated with a first voltage domain, and supply voltages associated with a second voltage domain, and outputs a second signal that is associated with the second voltage domain. The bias circuit generates the bias voltage that is indicative of the duty cycle of the second signal, and provides the bias voltage to the control circuit to control the duty cycle of the second signal. The duty cycle of the second signal is controlled such that a difference between a duty cycle of the first signal and an inverse of the duty cycle of the second signal is less than a tolerance limit.

Abstract: A system and method to detect the presence of conductive foreign objects for a multi-coil wireless power system is described. A wireless power receiver resonant circuit quality information may be obtained without any costly hardware or termination of power delivery to the power receiver load. The power receiver free-running coil current or voltage may be measured during a very short time window. In this time window, the measurement may be unaffected by transmitter and receiver load due to the transmitter coil disconnection and because the wireless power receiver has sufficient DC-bus capacitance.

Abstract: In an integrated circuit, a first current source is coupled between a first supply voltage and a first node. An output stage includes a first current steering PMOS transistor coupled to the first node, a first current steering NMOS transistor including a first current electrode coupled to the first current steering PMOS transistor at a second node, a second current steering PMOS coupled to the first node, and a second current steering NMOS transistor including a first current electrode coupled to the second current steering PMOS transistor at a third node. Voltage at the second node is used to drive a gate of the second current steering PMOS transistor, and voltage at the third node is used to drive a gate of the first current steering PMOS transistor. First and second programmable slew rate pre-drivers provide outputs to the gates of the first and second current steering NMOS transistors, respectively.

Abstract: A circuit module (e.g., an amplifier module) includes a module substrate, a thermal dissipation structure, a semiconductor die, encapsulant material, and an interposer. The module substrate has a mounting surface and a plurality of conductive pads at the mounting surface. The thermal dissipation structure extends through the module substrate, and a surface of the thermal dissipation structure is exposed at the mounting surface of the module substrate. The semiconductor die is coupled to the surface of the thermal dissipation structure. The encapsulant material covers the mounting surface of the module substrate and the semiconductor die, and a surface of the encapsulant material defines a contact surface of the circuit module. The interposer is embedded within the encapsulant material. The interposer includes a conductive terminal with a proximal end coupled to a conductive pad of the module substrate, and a distal end exposed at the contact surface of the circuit module.

Abstract: A four-phase (or multi-phase) generation circuit, related method of operation, and transceivers or other systems utilizing such a circuit, are disclosed herein. In one example embodiment, the circuit includes two input ports respectively configured to receive positive and negative differential input signals, and four output ports respectively configured to output first, second, third and fourth output signals, respectively, the second, third, and fourth output signals being respectively phase-shifted relative to the first output signal by or substantially by 90, 180, and 270 degrees. Also, the circuit includes four SR latches respectively including output terminals that are respectively coupled to the respective output ports. Further, the circuit includes two tunable delay circuits respectively coupled at least indirectly between the input ports and latches, and two comparison circuits configured to output respective feedback signals.

Abstract: A memory includes an array of resistive memory cells and circuitry for setting a write parameter for improving write effectiveness to the cells of the memory array. The circuitry performs a write parameter setting routine that determines a midpoint resistance of a memory state of cells of the array and determines a write efficiency of a weak write operation to cells of the array. Based on the determined midpoint resistance and the determined write efficiency, the circuit sets a write parameter level for subsequent writes to cells of the array.

Abstract: A radio frequency identification (RFID) transponder includes a current control module for controlling a current consumption of a memory based on an amount of available power, and a control logic for controlling a memory operation in response to the control of the current consumption by the current control module. The RFID transponder further includes a power detector that is configured to continuously monitor and detect the amount of available power and output a power-dependent control signal. The power-dependent control signal is used by the RFID transponder to control the current consumption of the memory in dependence on the available power.

Abstract: Various embodiments relate to a converter controller configured to control a resonant converter, including: an integrator configured to receive a current measurement signal from a current measurement circuit in the resonant converter and to produce a capacitor voltage signal indicative of the voltage at the resonant capacitor; a control logic configured to produce a high side driver signal, a low side driver signal, a symmetry error signal based upon the capacitor voltage signal and the current measurement signal; and a symmetry controller configured to produce a symmetry correction signal based upon the symmetry error signal, wherein the symmetry error signal is input into the integrator to control the duty cycle of the high side driver signal and the low side driver signal, wherein the high side driver signal and the low side driver signal control the operation of the resonant converter.

Abstract: A signal generator includes a first voltage generator, a second voltage generator, an operational amplifier, and an oscillator. The first voltage generator generates a first voltage, and the second voltage generator generates a second voltage. The operational amplifier generates an amplified error signal based on the first voltage and the second voltage, and the oscillator generates a periodic signal based on the amplified error signal. The first voltage generator and the second voltage generator are configured to generate their respective voltages based on the periodic signal. As a result, frequency deviation in the periodic signal may be corrected, for example, without increasing the source current of the oscillator or the gain of the operational amplifier. Also, improved phase noise performance may also be achieved through an increase in loop gain.

Abstract: An enabling system that includes a controller and processing circuitry, is configured to enable an external oscillator that operates in one of single-ended, differential, and crystal modes. To enable the external oscillator, the controller is configured to detect a mode of operation of the external oscillator, and the processing circuitry is configured to operate in the detected mode. The controller detects the mode of operation of the external oscillator by sequentially initializing the processing circuitry to operate in the single-ended, differential, and crystal modes, and determining whether the current operating mode of the processing circuitry is same as the mode of operation of the external oscillator based on a clock signal outputted by the processing circuitry during the corresponding mode.

Abstract: A mechanism is provided for determining an unambiguous direction of arrival (DoA) for radio frequency (RF) signals received by a sparse array. A DoA angle domain is split into hypothesis regions. The hypothesis regions are derived from the phase differences of the antenna element pairs used for the DoA angle estimate. In each hypothesis region, the ambiguous phase of antenna element pairs is unwrapped according to expected wrap-around. After unwrapping the phase, for each hypothesis region, a phasor is calculated by combining the individual antenna element pair phasors. The hypothesis region that obtains the phasor with a largest amplitude is selected as the most likely DoA region and the phase of the winning phasor is used as an unambiguous estimate for the DoA angle.

Abstract: A wireless receiving device comprises a low-density parity check (LDPC) decoding circuit, comprising a circular shifter constructed and arranged to simultaneously process multiple code words of a parity check matrix configured for different wireless communication standards, including performing a cyclic shift operation of the multiple code words to align with one or more requisite check nodes of a decoder and a logic circuit at an output of the circular shifter constructed and arranged for a matrix larger than the parity check matrix and that includes components having excess hardware due to the construction and arrangement for the larger matrix to decode the multiple code words of the smaller parity check matrix for output to the one or more requisite check nodes.

Abstract: An intelligent transportation system (ITS) for a vehicle is described. The ITS includes: a packet count estimator arranged to receive broadcast ITS transmissions from a plurality of neighbouring vehicles and provide an indication of a number of packets received from the plurality of neighbouring vehicles, where the indication includes at least an information length and a data rate of the received packets; a fair resource allocator circuit operably coupled to the packet count estimator and configured to adjust at least one ITS broadcast transmission parameter of the ITS based on the indication of the number of received packets; and a transmitter operably coupled to the fair resource allocator circuit and configured to broadcast at least one ITS message using the adjusted at least one ITS broadcast transmission parameter.

Abstract: Various embodiments relate to a skew detector circuit, including: a logic circuit having two inputs configured to generate a logic 1 output when the two inputs have a logic 0 value and generator a logic 0 output when the two input have a logic 1 value; a first level shifter configured to increase the output of the logic circuit to a higher voltage; a second level shifter configured to increase the output of the first level shifter to a higher voltage; and a voltage regulator configured to produce a first voltage for the logic circuit, a second voltage for the first level shifter, and a third voltage for the second level shift.

Abstract: Embodiments of an electrostatic discharge (ESD) protection device and a method for operating an ESD protection device are described. In one embodiment, an ESD protection device includes a primary ESD protection unit electrically connected to a first node and to a second node and configured to shunt current in response to an ESD pulse received between the first and second nodes and a secondary ESD protection unit electrically connected to the primary ESD protection unit and to the second node and configured to shunt current in response to the ESD pulse to keep an output voltage of the ESD protection device to be within a safe operating voltage range of a device to be protected. Other embodiments are also described.

Abstract: A method and apparatus are provided for controlling a sensorless multi-phase permanent magnet (PM) motor by sensing induced motor terminal voltages from the PM motor while the rotor is spinning, generating an input voltage vector signal from the plurality of induced motor terminal voltages, projecting the input voltage vector signal to a transformed voltage vector signal which does not include DC-offset components by using a Clarke transformation without a zero component that is applied to the input voltage vector signal, and estimating an initial rotor position of the rotor from the transformed voltage vector signal, wherein said sensing, projecting, and estimating are performed while a power converter for the sensorless multi-phase PM motor is disabled.

Abstract: An inductor and a method of making an inductor. The inductor includes a stack of dielectric layers. The inductor also includes a plurality of metal levels comprising patterned metallic features of the inductor. Each metal level is located at an interface between adjacent dielectric layers in the stack. The patterned metallic features include a first plurality of inductor windings arranged in a substantially flat spiral in one of the metal levels. The patterned metallic features also include a second plurality of inductor windings in which each winding is located in a respective one of the plurality of metal levels. The first plurality of windings is connected in series with the second plurality of windings.

Abstract: A semiconductor device and a method of making a semiconductor device. The device includes an emitter. The device also includes a collector. The device further includes a base stack. The base is located between the emitter and the collector. The base stack includes an intrinsic base region. The device further includes a base electrode. The base electrode comprises a silicide. The silicide of the base electrode may be in direct contact with the base stack. The device may be a heterojunction bipolar transistor.

Abstract: A human-machine-interface system comprising: register-file-memory, configured to store input-data; a first-processing-element-slice, a second-processing-element-slice, and a controller. Each of the processing-slices comprise: a register configured to store register-data; and a processing-element configured to apply an arithmetic and logic operation on the register-data in order to provide convolution-output-data. The controller is configured to: load input-data from the register-file-memory into the first-register as the first-register-data; and load: (i) input-data from the register-file-memory, or (ii) the first-register-data from the first-register, into the second-register as the second-register-data.

Abstract: A defrosting system includes an RF signal source, two electrodes proximate to a cavity within which a load to be defrosted is positioned, a transmission path between the RF signal source and the electrodes, and an impedance matching network electrically coupled along the transmission path between the output of the RF signal source and the electrodes. The system also includes power detection circuitry coupled to the transmission path and configured to detect reflected signal power along the transmission path. A system controller is configured to modify, based on the reflected signal power, values of variable capacitors of the impedance matching network to reduce the reflected signal power. The impedance matching network may be a single-ended network or a double-ended network.