Abstract: The invention relates to a non-volatile memory device comprising: an input for providing external data (D1) to be stored on the non-volatile memory device; and a first non-volatile memory block (100) and a second non-volatile memory block (200), the first non-volatile memory block (100) and the second non-volatile memory block (200) being provided on a single die (10), wherein the first non-volatile memory block (100) and second non-volatile memory block (200) are of a different type such that the first non-volatile memory block (100) and the second non-volatile memory block (200) require incompatible external attack techniques in order to retrieve data there from, the external data (D1) being stored in a distributed way (D1?, D1?) into both the first non-volatile memory block (100) and the second non-volatile memory block (200). The invention further relates to method of protecting data in a non-volatile memory device.

Abstract: Consistent with an example embodiment, there is a bipolar transistor with a reduced collector series resistance integrated in a trench of a standard CMOS shallow trench isolation region. The bipolar transistor includes a collector region manufactured in one fabrication step, therefore having a shorter conductive path with a reduced collector series resistance, improving the high frequency performance of the bipolar transistor. The bipolar transistor further includes a base region with a first part on a selected portion of the collector region (6, 34), which is on the bottom of the trench, and an emitter region on a selected portion of the first part of the base region. A base contact electrically contacts the base region on a second part of the base region, which is on an insulating region. The collector region is electrically contacted on top of a protrusion with a collector contact.

Abstract: An electronic circuit (10) for controlling a capacitive pressure sensor (1), which capacitive pressure sensor (1) comprises a plate electrode capacitor (C) with a capacity that varies in dependence on pressure changes exerted on a deflectable diaphragm (2) forming one plate electrode of the capacitor (C), wherein the electronic circuit (10) comprises a DC voltage source (12) being adapted to generate a DC bias-voltage (UDC) to be applied across the electrodes of the capacitor (C), an AC voltage source (13) being adapted to generate an AC voltage signal (UAC) to be applied across the electrodes of the capacitor (C) and a controller (18) being adapted to receive an output signal (OUT) of the capacitor (C) and to control the DC voltage source (12) such that the DC bias-voltage (UDC) applied to the capacitor (C) adopts a value that maintains the capacity of the capacitor (C) at a desired value.

Abstract: A switching amplifier (200; 300; 400; 500) comprising: a switch (202; 302) configured to electrically connect and disconnect a first pin (202a; 302a) of the switch (202; 302) to a second pin (202b; 302b) of the switch (202; 302) in accordance with a pulse width modulated input signal (216; 316; 516). The second pin (202b; 302b) is connected to a ground connector (204; 304). The switching amplifier also comprises a feed inductor (206; 306; 406) connected between a voltage supply connector (208; 308) and the first pin (202a; 302a) of the switch (202; 302), and a circuit (210; 310; 522) comprising a variable component having a variable imaginary impedance. The circuit (210; 310; 522) is connected between the first pin (202a; 302a) of the switch (202; 302) and an output connector of the amplifier (212; 312.

Abstract: A receiver system to receive an orthogonal frequency division multiplexing (OFDM) symbol of a certain spectrum efficiency. The receiver system includes a guard interval remover, a memory device, and a pulse shaper. The guard interval remover removes a guard interval from the OFDM symbol received by the receiver. The memory device stores a pulse shaping algorithm. The pulse shaper performs the pulse shaping algorithm to substantially maintain the certain spectrum efficiency in conjunction with the utilization of a Nyquist pulse shape with an excess bandwidth ?1.0.

Abstract: A high bandwidth circuit is segmented into a plurality of portions, each portion for implementation on a corresponding semiconductor chip, an arrangement of one or more die bond pads for each corresponding chip is generated, and a chip location for each corresponding chip is generated, given package and given package I/O arrangement is generated, the generation of the die bond arrangements and the chip position being relative to given chip package parameters, and being generated to establish bond wire lengths meeting given characteristic impedance parameters. Boundary parameters for generating the segmenting are provided, including a bound on the number of portions and optionally a including bound on the area parameters of the corresponding semiconductor chips.

Abstract: Power consumption of near-field communication devices is regulated by waking the device for communications when a potential external near-field device is detected, and by adjusting the resonant antenna circuit to account for the detected change in antenna environment. Such near-field communication devices, which may be used to detect and read external RFID tags, include a resonant loop antenna circuit having an antenna and a variable component, the antenna circuit being tunable by adjusting the variable component. The antenna has a target range of operation for near-field communication, and an inductance that is susceptible to interference that can alter the target range.

Abstract: In a controller (CC2) for controlling a synchronous rectification switch (S2), the controller (CC2) comprises a sensing circuit (SRL) for sensing an output (D2) of the synchronous rectification switch (S2) at an end of a blanking time to obtain a sense signal (Q), and a control signal generating circuit (AND1) for generating a control signal (G2) for the synchronous rectification switch (S2) in dependence on the sense signal (Q).

Abstract: A mobile station (100) in a mobile communication system obeys commands received from a serving base station (300) to decrease its transmission rate, and obeys commands received from the serving base station (300) to increase its transmission rate except when a predetermined time period is in progress. It obeys commands received from a non-serving base station (200, 400) to decrease its transmission rate, it initiates the predetermined time period in response to receiving such commands, and it terminates the predetermined time period in response to a further command from the same non-serving base station (200, 400).

Abstract: An integrated circuit comprising a plurality of CMOS modules (10) connected in series with each other, each module (10) being connected between first and second reference lines (Vdd, Vss). A first transistor (54) is provided between at least one of the modules (10) and the first reference line (Vdd) and a second transistor (52) is provided between one of the modules (10) and the second reference line (Vss) and capacitors (C25, C26) are provided in parallel with the transistors (52, 54) such that they are driven as current sources (I1, I2). As a result power dissipation and leakage current is reduced.

Abstract: An electronic circuit (100) is disclosed for processing signals (20L, 20R) originating from respective signal recorders (20) integrated in respective earpieces of a headset. The electronic circuit comprises a first input for receiving a signal (20L) from the signal recorder of the ear piece intended for a left ear of a wearer of the headset, said signal relating to a blood pressure pulse (200) of said wearer; a second input for receiving a further signal (20R) relating to said blood pressure pulse from the signal recorder of the ear piece intended for a right ear of the wearer; a detection unit (110, 120) for detecting the order in the signal and the further signal are recorded by said respective signal recorders and for comparing the detected order with a correct order; and a signal adaptation unit (130) for adapting an output signal (30L, 30R) in response to the detection unit signaling a detection of an incorrect order of the signal and the further signal.

Abstract: Device for generating a message authentication code for authenticating a message, wherein the message is divided in blocks (M) with a specified block length, the device comprising a generating unit for generating the message authentication code based on a message by using a block cipher algorithm, and an encrypting unit for performing an exclusive disjunction on the last block with a first key (K1, K2) and for performing an exclusive disjunction on the first and/or the last block additionally with a second key (K3, K4) for generating the message authentication code.

Abstract: A method of obfuscating a code is provided, wherein the method comprises performing a first level obfuscating technique on a code to generate a first obfuscated code, and performing a second level obfuscating technique on the first obfuscated code. In particular, the code may be a software code or a software module. Furthermore, the first level obfuscating technique and the second obfuscating may be different. In particular, the second level obfuscating technique may perform a deobfuscation.

Abstract: A method of manufacturing a semiconductor device having gate electrodes of a suitable work function material is disclosed. The method comprises providing a substrate (100) including a number of active regions (110, 120) and a dielectric layer (130) covering the active regions (110, 120), and forming a stack of layers (140, 150, 160) over the dielectric layer. The formation of the stack of layers comprises depositing a first metal layer (140), having a first thickness, e.g.

Abstract: A method is disclosed of manufacturing an integrated circuit. The method comprises providing a substrate (100) comprising a source region (102) and a drain region (104) separated by a channel region (106, 406), said channel region being covered by a gate stack separated from the channel region by a dielectric layer (110), the gate stack comprising a metal portion (112) over the dielectric layer (110) and a polysilicon portion (116) over the metal portion (112); implanting an oxide reducing dopant (130) into the polysilicon portion (116); depositing a silicidation metal (140) over the implanted polysilicon portion (116); and converting the implanted polysilicon portion (116) into a suicide portion. By fully converting the polysilicon portion (116) into a suicide portion, the dopant (130) is ‘snow-ploughed’ towards the interface between the metal portion (112) and the polysilicon portion (116) where it reacts with any oxide formed at said interface.

Abstract: A system and method for frame rate conversion using multi-resolution temporal interpolation utilizes motion estimation on input images to produce at least one motion vector and temporal interpolation on the input images in at least one spatial resolution that is determined by a characteristic of the at least one motion vector.

Abstract: A radio frequency (RF) communication device (1, 1?, 10) has data transmission means and data receiving means. The data transmission means comprise load modulating means (3) being adapted to receive a radio frequency carrier signal (CS1, CS2) emitted by another RF communication device (1, 1?, 10) and to modulate the RF carrier signal (CS1, CS2) by means of load modulation in accordance with data to be sent. The data receiving means comprise a RF frequency carrier signal generator (4) being adapted to emit a radio frequency carrier signal (CS1, CS2) and load demodulating means (5) being connected to an emission path (4a) of the radio frequency carrier signal and demodulating the radio frequency carrier signal (CS1, CS2) when it has been load modulated by another RF communication device (1, 1?, 10).

Abstract: The present invention relates to a level shifter circuit (20) for transistors requiring high voltage, such as nonvolatile memories. In the circuit configuration, the drain- to-source voltage across the NMOS transistors (Q1, Q4) can be substantially equal to the power supply voltage (VPP) according to the input voltage level at the complementary input terminals (IN, INB). For alleviating such a voltage stress, the source potential of each NMOS transistor is increased according to the input voltage level. Thus, the source of the transistor at the OUT side is biased by the input signal at the input terminal (IN) and the source of the transistor at the IN side is biased by the complementary input signal at the corresponding terminal (INB). Hot-carrier degradation and leakage of the load current flowing through from the power supply voltage (VPP) to the reference voltage (VSS) can be then reduced.

Abstract: A line-based one-dimensional system and method for video and graphic compression compresses an image data block that contains image data values from one or more neighboring pixels. The system and method involves compressing an image data sample of the image data block using multiple different compression techniques to generate multiple compression results, selecting one of the compression results, and compressing a next image data sample using the multiple different compression techniques and a compression error from the selected one of the compression results.

Abstract: A system and method for video compression utilizes non-linear quantization and modular arithmetic computation to perform differential coding on multiple blocks of video data and uses a result of the differential coding to generate a codeword.