Abstract: In an NFC mobile communication device (3) an operating system, such as a JAVA operating system (J2ME), is able to start software applications (6) identifiable by application identifications (AID). The mobile communication device (3) is equipped with a secure memory device (2), e.g. configured as a SmartMX card, which comprises a first memory portion (2a) configured as a MIFARE memory. The mobile communication device (3) comprises NFC means (5) adapted to trigger a hardware interruption (INT), when the first memory portion (2a) has been accessed by an external RFID reader (1). The hardware interruption (INT) is detected by the operating system (J2ME) and causes it to access a pre-defined sector (5) of the first memory portion (2a), to read information from said sector (5) which is representative for an application identification (AID) and to start the software applications (6) associated to it.

Abstract: An output stage (1) for a digital RF transmitter is provided. The output stage comprises: an input adapted to receive an input signal (RFin, b7-b0) to be transmitted; a plurality N of power amplification sections (S1, S2, S3, S4); and an output (A, B) providing an output voltage signal. Each of the N power amplification sections (S1, S2, S3, S4) is arranged to receive the input signal (RFin, b7-b0) and comprises a transformer (T1, T2, T3, T4) adapted to provide a respective output signal. Each transformer comprises a primary stage and a secondary stage; the secondary stages of the transformers (T1, T2, T3, T4) of the N power amplification sections (S1, S2, S3, S4) are combined such that a combined output voltage signal of the output stage is provided. The N power amplification sections (S1, S2, S3, S4) are adapted such that the input signal (RFin, b7-b0) is latched by clock signals (clock1, clock2, clock3, clock4) comprising different phases.

Abstract: In an embodiment of a converter, a first oscillator provides switching signals for switching between charging and discharging of a capacitor, and a second oscillator is configured to add an offset voltage or a feedback-current-dependent voltage to a sawtooth waveform generated by the second oscillator switched in synchronism with the first oscillator.

Abstract: A planar inductive unit having at least one operating frequency is provided. The inductive unit comprises at least one inductor winding (120) having a first width (121) and a centre (122) and being arranged in a first plane. The inductive unit furthermore comprises at least one ground path (200) having a first section (205) extending in the first plane and at least a second section (210) with a second width (211) extending in at least a second plane.

Abstract: An acoustic material is intended to be mounted behind a loudspeaker 8 to decrease the resonant frequency and/or to reduce the back volume. The acoustic material includes a woven or non-woven fabric which supports highly porous particles or fibers such as particles of carbon black. The woven or non-woven is thin and light to avoid damping sound, whilst still being capable of retaining the porous material. The use of a flexible acoustic material allows the material to be more easily included with loudspeakers in portable mobile devices.

Abstract: Method for setup of parameter values in a RF power amplifier circuit arrangement (200), wherein the amplifier circuit arrangement (200) comprises a first (210) and a second (220) amplification branch and is operated in an out-phasing configuration for amplification of RF input signals with modulated amplitude and modulated phase and respective circuit arrangements are disclosed. According to a first aspect a re-optimization of the dead-time or conversely the duty-cycle, respectively, the phase of the output signal after the combiner can be kept linear with respect to the out-phasing angle. Further, according to a second aspect, additionally to introduction of an optimally chosen dead-time, a non-coherent combiner (Lx, Lx*) can reduce crowbar current and switching losses due the output capacitance (Cds). Furthermore, according to a third aspect the reactive compensation can, additionally or alternatively, be controlled by operating both amplification branches at different duty-cycles.

Abstract: The invention relates to electronic device having an operation temperature range, wherein the electronic device comprises a tunable capacitor (CST) comprising a first electrode (BE), a second electrode (TE), and a dielectric (FEL) arranged between the first electrode (BE) and the second electrode (TE). The dielectric (FEL) comprises dielectric material (FEL) having a value of a relative dielectric constant (?r) varying at least within the operation temperature range. The electronic device further comprises a temperature varying means (RES) being thermally coupled to the tunable capacitor for providing a temperature of the dielectric (FEL) causing a predetermined capacitance of the tunable capacitor (CST). The invention, which relies on the idea of varying temperature to vary a capacitance of a capacitor stack, provides an alternative tunable capacitor type for the known types.

Abstract: A method of achieving frequency doubled lithographic patterning is described. An optical pattern (16) having a first period (p1) is used to expose conventional acid-catalysed photoresist (18) on substrate (20), leaving regions of high exposure (24), regions of low exposure (26) and intermediate regions (22). Processing proceeds leaving regions (24) which received high exposure very polar, i.e. hydrophilic, regions (26) of low exposure very apolar, i.e. hydrophobic, and the intermediate regions having intermediate polarity. A developer of intermediate polarity such as propylene glycol methyl ether acetate is then used to dissolve only the intermediate regions (22) leaving photoresist patterned to have a pitch (p2) half that of the optical period (p1). Alternatively, the photoresist is removed from the apolar and polar regions leaving only the intermediate regions (22) again with the same pitch (p2) half that of the optical period (p1).

Abstract: The present invention provides a method of lithographic patterning in order to the strength of the patterned photoresist. The method comprises: applying to a surface to be patterned a photoresist (18) comprising a polymer resin, a photocatalyst generator which generates a catalyst on exposure to actinic radiation, and a quencher; and exposing the photoresist (18) to actinic radiation through a mask pattern (12). This is followed, in either order, by carrying out a post-exposure bake; and developing the photoresist (18) with a developer to remove a portion of the photoresist which has been exposed to the actinic radiation. The polymer resin is substantially insoluble in the developer prior to exposure to actinic radiation and rendered soluble in the developer by the action of the catalyst, and wherein the polymer resin is crosslinked by the action of the quencher during the bake.

Abstract: A receiver circuit has a chain of stream processing circuits (10a-c)—having control parameter inputs for receiving control parameter values. To facilitate design of circuits that receive data with a variable block size, an included control circuit (14) selects block sizes of blocks of samples in the respective streams of a plurality of the stream processing circuits (10a-c), a control parameter value for each particular block. The control circuit transmits instructions specifying the selected block sizes and control parameter values to local control circuits (11). Each local control circuit is coupled to the control circuit (14) and the control input of a respective corresponding stream processing circuit (10a-c). Each local control circuit (11) receives at least part of the instructions and applies parameter values from the instructions to its corresponding stream processing circuit (10a-c). The local control circuit (11) controls timing of control parameter updates using block sizes from the instructions.

Abstract: The present invention relates to an asynchronous data buffer for transferring m data elements of a burst-transfer between two asynchronous systems. The asynchronous data buffer comprises a data memory for storing m data elements of a data burst and a valid bit memory for storing m input valid bits corresponding to the m data elements. Input control logic circuitry generates the m input valid bits and controls storage of the same and the m data elements. After storage of the m input valid bits an input control signal is provided for inverting the input valid bits of a following data burst. Therefore, after each burst-transfer of m data elements the input valid bit is inverted, automatically rendering all data elements of a previous burst-transfer invalid.

Abstract: A method of making a semiconductor device includes forming shallow trench isolation structures in a semiconductor device layer. The shallow trench isolation structures are U- or O- shaped enclosing field regions formed of the semiconductor device layer which is doped and/or silicided to be conducting. The semiconductor device may include an extended drain region or drift region and a drain region. An insulated gate may be provided over the body region. A source region may be shaped to have a deep source region and a shallow source region. A contact region of the same conductivity type as the body may be provided adjacent to the deep source region. The body extends under the shallow source region to contact the contact region.

Abstract: An electronic circuit contains groups of flip-flops (12a-c), coupled to data terminals (11a-c) of the circuit and to a functional circuit (10). Each group (12a-c) has a clock input for clocking the flip-flops of the group. Each group (12a-c) can be switched between a shift configuration and a functional configuration, for serially shifting in test data from the data terminals and to function in parallel to supply signals to the functional circuit (10) and/or receive signals from the functional circuit (10) respectively. A test control circuit (16) can be switched between a functional mode, a test shift mode and a test normal mode. The test control circuit (16) is coupled to the groups of flip-flops (12a-c) to switch the groups to the functional configuration in the functional mode and to the shift configuration in the test shift mode. A clock multiplexing circuit (15a-c, 18) has inputs coupled to the data terminals (11a-c) and outputs coupled to clock inputs of the groups (12a-c).

Abstract: In an electroacoustic transducer (21) with a stationary transducer part (23) and with a membrane configuration (17) comprising a membrane (15) and a handling ring (1) for the membrane (15) connected with the membrane (15), the membrane configuration (17) is connected with the stationary transducer part (23) via the handling ring (1), and the handling ring (1) and membrane (15) are connected together via an interlocking connection.

Abstract: An integrated HF-amplifier has an input bond pad, cells displaced in a first direction, and an output bond pad. Each has a amplifier with input pad, active area, and output pad. The active area is arranged in-between the input and output pads, and the input pad, active area, and output pad are respectively displaced in a second direction substantially perpendicular to the first direction. A first network interconnects input pads of adjacent cells, and extends in the first direction. A second network interconnects output pads of adjacent cells, and extends in the first direction. The first and second networks obtain an output signal at the output bond pad having for all interconnected cells an equal phase shift and amplitude for a same input signal at the input bond pad. At particular bias and phase shift conditions this provides a Doherty amplifier with improved efficiency at power back off.

Abstract: A phase-change-material memory cell is provided. The cell comprises at least one patterned layer of a phase-change material, and is characterized in that this patterned layer comprises at least two regions having different resistivities. If the resistivity of the phase-change material is higher in a well-defined area with limited dimensions (“hot spot”) than outside this area, then, for a given current flow between the electrodes, advantageously more Joule heat will be generated within this area compared to the area of the phase-change material where the resistivity is lower.

Abstract: The present invention relates in general to transferring the envelope information of a polar modulated signal to a varying pulsewidth signal, while the phase modulation is direct transferred to the phase modulation of this PWM signal. Accordingly, the resultant signal is a PWM-PPM-signal. Such a signal can efficiently amplified by use of switching amplifying stages. By the present invention four pre-distorted baseband signals are applied basically to 4 linear RF mixers and a two adders, which are, the only needed external RF building blocks to build the modulator according to the invention. That is, the basic idea of the invention resides in the way of modulation of the four baseband signals and the way of combining of the RF modulated signals.

Abstract: A method of manufacturing an I-MOS device includes forming a semiconductor layer (2) on a buried insulating layer (4). A gate structure (23) including a gate stack (14) is formed on the semiconductor layer, and used to (5) self align the formation of a source region (28) by implantation. Then, an etch step is used to selectively etch the gate structure (23) and this is followed by forming a drain region (36) by implantation. The method can precisely control the i-region length (38) between source region (28) and gate stack (14).

Abstract: Receivers (1) for receiving radio frequency signals need automatic gain control alignment by hand during the production process, which makes the production process more expensive, more time-consuming and less reliable (insight). By (basic idea) providing receivers (1) with a first and a second gain controller (38, 54) for controlling the gains of a first (radio frequency) and a second (intermediate frequency) stage (3, 5) independently from each other, alignment by hand is no longer necessary, which results in a less expensive, less time-consuming and more reliable production process. The gain controllers (38, 54) have gain detectors (41, 59) for detecting output signals, and gain generators (40, 58) for generating gain control signals, and control inputs (42, 60) for receiving the same reference level signal (REF) for controlling the gains in relation to the same reference level.

Abstract: A multi-clock system-on-chip (D) comprises i) a core (CE) comprising asynchronous clock domains provided for exchanging test data therebetween, ii) a clock generator unit (CGU) arranged for delivering primary clock signals (clk1-clko) for at least some of the clock domains, and iii) clock control modules (CCl-CCo), arranged respectively for defining the functional clock signals from the primary clock signals and from control signals (intended for setting the clock control modules (CCl) in a normal mode allowing test data transmission from the corresponding emitter clock domain to at least one receiver clock domain or a shift mode forbidding such a test data transmission).