Abstract: A test-communication path is provided between chips in a multi-chip package. Externally-accessible JTAG input and output pins are provided to a first chip in the multi-chip package, and this first chip is configured to allow signals received on these JTAG pins to be routed to other chips in the multi-chip package. Control signals provided to the first chip control the routing of the JTAG signals to each chip.

Abstract: To enable a method and a base chip (200) for monitoring, by means of at least one base chip (200), the operation of at least one microcontroller unit (300) that is intended for at least one application and is associated with a system (100) to be further developed in such a way a reset of the microcontroller unit (300) only takes place under defined conditions, it is proposed that a reset (R) of the microcontroller unit (300) is caused if at least one special sequence, and particularly at least one drive or access sequence assigned to the reset operation (R), is applied to the base chip (200).

Abstract: A communications arrangement is implemented for packet data communications control. According to an example embodiment of the present invention, a communications arrangement (100), such as a PCI Express type arrangement, carries out separate arbitration functions (112, 116, 117, 118) for ordering packet data. One of the arbitration functions (112) orders the packet data in accordance with protocol standards (e.g., to meet PCI Express standards when implemented with a PCI Express system). The other arbitration function (116, 117, 118) orders the packet data in accordance with performance standards while maintaining compliance with the protocol standards.

Abstract: The invention relates to a semiconductor device (10) with a semiconductor body (12) comprising a bipolar transistor with an emitter region, a base region and a collector region (1, 2, 3) of, respectively, a first conductivity type, a second conductivity type opposite to the first conductivity type, and the first conductivity type. One of the emitter or collector regions (1, 3) comprises a nanowire (30). The base region (2) has been formed from a layer (20) at the surface of the semiconductor body (12); the other one (3, 1) of the emitter or collector regions (1, 3) has been formed in the semiconductor body (12) below the base region (2). The emitter or collector region (1, 3) comprising the nanowire (30) has been provided on the surface of the semiconductor body (12) such that its longitudinal axis extends perpendicularly to the surface.

Abstract: A carrier assembly for receiving an RFID transponder chip has an attachment side for being attached to a consumer device and an operation side for receiving an RF signal in operational use of the RFID transponder chip.

Abstract: A method for secure data reading and a data handling system is provided. The method protects the data reading from fault attacks by repeating read request in an interleaved manner, in particular the method comprises the steps of (M200) dispatching a first read request; (M400) dispatching a second read request; (M600) dispatching a further first read request; and (M1000-a) producing an anomaly signal if a first result produced by the memory in response to the first read request does not agree with a further first result produced by the memory in response to the further first read request.

Abstract: A method is provided of charging a mobile device by a charger device, comprising transmitting and receiving a charging current via the Hot Plug Detect (HPD) pin of an HDMI cable connected between the mobile device and the charging device. The HDMI source device (the mobile device) and the HDMI sink device (the charger device) are also provided.

Abstract: The invention provides a method for cycle-by-cycle control of a LED current (ILED) flowing through a LED circuit arrangement (LEDCIRC) at a mean LED current level. The method comprises a) establishing a converter current (IL), b) establishing an oscillation of the converter current (IL) between substantially a valley current level and substantially a peak current level, c) feeding the LED circuit arrangement (LEDCIRC) with the converter current (IL) as the LED current during a part of an oscillation cycle of the oscillation of the converter current, d) determining a current level correction for compensating a current level error between an integral over an oscillation cycle of the LED current and a reference, the reference being representative of the mean LED current level, and e) adjusting at least one of the valley current level and the peak current level with the current level correction for use in a successive cycle of the oscillation of the converter current.

Abstract: A processing circuit has functional units (10a-c) configured to perform operations each in response to a respective command. The functional units (10a-c) are configured to execute at least one of the operations with a selectable level of susceptibility to incurring an error during execution. Different functional units may be provided, designed to execute the same operation with different levels of susceptibility at the cost of more circuit area, power consumption or execution time in the case of less susceptibility. The less susceptible functional unit may comprise additional error correction circuits, or more pipeline stages for example. The program directs commands to execute the operation to different functional units according to the required level of susceptibility. High level programs may be provided wherein variables are declared with a specified level of reliability. These declarations may be used during compilation to select how instructions will be executed.

Abstract: A method for installing linked MIFARE applications (TK1-A, TK1-B, TK1-C) in a MIFARE memory (MM) being configured as a MIFARE Classic card or an emulated MIFARE Classic memory comprises storing the first linked MIFARE application (TK1-A) in a first free sector of the MIFARE memory, storing the second linked MIFARE application (TK1-B) in a second free sector of the MIFARE memory and writing link information (LK) indicating this second sector in a link information memory location of the first sector where first linked MIFARE application (TK1-A) has been stored, and repeating the steps of storing linked MIFARE applications and writing link information (LK) until the last linked MIFARE application (TK1-C) has been stored.

Abstract: The invention relates to a system for providing fault tolerance for at least one micro controller unit, hereinafter called MCU (10). The MCU receives information from at least one sensor (11) coupled to the MCU (10) and outputs information to at least one actuator (12) coupled to the MCU (10). To provide a system for controlling or influencing the fault tolerance or the error processing of at least one MCU without requiring a replication of software or hardware components and which is able to react differently on various events it is proposed to include a System Supervision unit (200), hereinafter called SSU (200), in the MCU (10).

Abstract: The present invention relates to an integrated circuit comprising a plurality of bitlines (b1) and a plurality of word-lines (w1) as well as a plurality of memory-cells (MC) coupled between a separate bit-line/word-line pair of the plurality of bit-lines (b1) and wordlines (w1) for storing data in the memory cell. Each memory cell (MC) comprises a selecting unit (T) and a programmable resistance (R). The value of the phase-change resistance (R) is greater than the value of a first phase-change resistance (Ropt) defined by a supply voltage (Vdd) divided by a maximum drive current (Im) through said first phase-change resistor (Ropt).

Abstract: The present invention relates to a data processing system is provided which comprises at least one first processing unit (CPU), at least one second processing unit (PU), at least one memory module (MEM), and an interconnect. The memory module (MEM) serves to store data from said at least one first and second processing unit (CPU, PU). The interconnecting means couples the memory module (MEM) to the first and second processing units (CPU, PU). In addition, an arbitration unit (AU) is provided for performing the arbitration to the memory module (MEM) of the first and second processing units (CPU, PU). The arbitration is performed on a time window basis. A first access time during which the second processing unit (PU) has accessed the memory module and a second access time which is still required by the second processing unit (PU) to complete its processing are monitored during a predefined time window by the arbitration unit (AU).

Abstract: An apparatus comprises a memory with a matrix (10) with rows and columns of memory cells. A read access circuit (14, 16, 18) executes a read command to read a retrieval unit comprising data from a row of the memory cells from the matrix (10) and to output data from the retrieval unit. A processing circuit (12) coupled to the read access circuit (14, 16, 18) is configured to execute an extra read operation involving issuing the read command, receiving the extra data (24), performing error detection on only the extra data (24), using an error detecting code in which the extra data is coded, conditionally performing error correction on the data from the extra data (24) using data from the retrieval unit including the payload data (22), according to an error correcting code in which the retrieval unit is coded, if the error detection indicates an error in the extra data (24).

Abstract: Consistent with an example embodiment, an integrated circuit device (IC) is assembled on a package substrate and encapsulated in a molding compound. There is a semiconductor die having a circuit pattern with contact pads. A package substrate having bump pad landings corresponding to the contact pads of the circuit pattern, has an interposer layer sandwiched between them. The interposer layer includes randomly distributed mutually isolated conductive columns of spherical particles embedded in an elastomeric material, wherein the interposer layer is subjected to a compressive force from pressure exerted upon an underside surface of the semiconductor die. The compressive force deforms the interposer layer causing the conductive columns of spherical particles to electrically connect the contact pads of the circuit pattern with the corresponding bump pad landings of the package substrate.

Abstract: Fabrication of a mono-crystalline emitter using a combination of selective and differential growth modes. The steps include providing a trench (14) formed on a silicon substrate (16) having opposed silicon oxide side walls (12); selectively growing a highly doped mono-crystalline layer (18) on the silicon substrate in the trench; and non-selectively growing a silicon layer (20) over the trench in order to form an amorphous polysilicon layer over the silicon oxide sidewalls.

Abstract: A comparator comprises a differential amplifier (T1, T2, T8, T9) having differential inputs (IN1, IN2) forming the comparator inputs, and a first and a second amplifier output (f1, f2) forming the comparator outputs of a first comparator stage, wherein the differential amplifier has first (T1, T8) and second (T2, T9) parallel branches. The comparator has a first current source circuit (32) defines a current to be driven through the differential amplifier, a second current source circuit (34) comprising a load driven by the first branch and a third current source circuit (36), comprising a load driven by the second branch. Circuitry (T6,T7) is provided for defining the voltage difference between the first and second amplifier outputs when the differential amplifier is in a stable state providing a differential output. This arrangement drives current through the two branches independently, so that the main transistors in each branch can be kept on to enable rapid response times.

Abstract: Methods, apparatus, systems and devices are implemented according to a number of embodiments. According to one such embodiment, a method of synchronizing a receiver to a timing and carrier frequency of a communication system is implemented. A set of predetermined possible synchronization patterns is detected in a received signal. Timing and structure information is generated specifying the occurrence of detected ones of said predetermined set of possible synchronization patterns in said received signal. Channel coefficient estimations of different receiving channels are derived from the timing and structure information. A carrier frequency offset is determined for the received signal based on a comparison of predetermined ones of said derived channel coefficient estimates.

Abstract: The invention proposes to divide a content to be transmitted via a network into a set of slices and to generate a set of files from this set of slices. The slices (or the files) are encrypted before downloading in such a way that the client cannot use the slice (or the file) before having acquired the associated decryption key. The invention thereby allows protecting a downloaded content on a slice-by-slice basis (or on a file-by-file basis) rather than protecting a downloaded content as a whole. The transmission (in download mode) between the server and the client is ruled by the HTTP protocol that is accepted by all firewalls and NAT. Consequently, the transmitted content is accessible for any client device that has access to the Web without restriction. Advantageously, the slices can be decoded independently of each other.

Abstract: A method for manufacturing a microelectronic package (1) comprises the steps of providing two parts (13, 14) comprising electrically insulating material such as plastic; providing members (21, 22, 23) comprising electrically conductive material; providing a microelectronic device (30); positioning the electrically conductive members (21, 22, 23) and the microelectronic device (30) on the electrically insulating parts (13, 14); and placing the electrically insulating parts (13, 14) against each other, wherein microelectronic device (30) and portions of the electrically conductive members (21, 22, 23) are sandwiched between the electrically insulating parts (13, 14). The electrically conductive members (21, 22, 23) are intended to be used for realizing contact of the micro-electronic device (30) arranged inside the package (1) to the external world.