Abstract: A pair of MOS transistors (10,12) are arranged as a potential divider. As the MOS transistors (10,12) pass from a weak inversion regime to a strong inversion regime, the voltage at the midpoint of the threshold divider changes from being substantially constant to varying. A difference amplifier (14) is used to detect this voltage, and a feedback loop (16) through a further transistor (18) is also provided.

Abstract: An energy converter is disclosed in which self oscillation mode operation is improved by a closed loop feedback control. The feedback control utilises the voltage error from the voltage valley in the drain voltage (Vdrain) of the converter switch (1), to determine an error (E(n)) in the time domain. Control circuitry (61, 62, 63) is used to minimise this time-domain error (E(n)) to optimise the control of the switch mode converter.

Abstract: The illumination system has a light source (1) with a plurality of light emitters (R, G, B). The light emitters comprise at least a first light-emitting diode of a first primary color and at least a second light-emitting diode of a second primary color, the first and the second primary colors being distinct from each other. The illumination system has a facetted light-collimator (2) for collimating light emitted by the light emitters. The facetted lightcollimator is arranged along a longitudinal axis (25) of the illumination system. Light propagation in the facetted light-collimator is based on total internal reflection or on reflection at a reflective coating provided on the facets of the facetted light-collimator. The facetted light-collimator merges into a facetted light-reflector (3) at a side facing away from the light source. The illumination system further comprises a light-shaping diffuser (17). The illumination system emits light with a uniform spatial and spatio-angular color distribution.

Abstract: A voltage reference connects to a voltage-to-current converter to generate a reference current dependent on the reference voltage. Outputs of a toggle-type flip flop connect to switching transistors controlling the reference current charging capacitors. The toggling of the flip-flop is controlled by comparing the capacitor voltages to the reference voltage, such that the toggle frequency is proportional to the time charging the capacitors. Optionally, temperature compensation data, representing a magnitude and direction rotation of the frequency versus temperature characteristic is stored and, based on a sensed temperature, retrieved to modify the reference current.

Abstract: A method of fabricating a self-aligned Schottky junction (29) in respect of a semiconductor device. After gate etching and spacer formation, a recess defining the junction regions is formed in the Silicon substrate (10) and a SiGe layer (22) is selectively grown therein. A dielectric layer (24) is then provided over the gate (14) and the SiGe layer (22), a contact etch is performed to form contact holes (26) and the SiGe material (22) is then removed to create cavities (28) in the junction regions. Finally the cavities (28) are filled with metal to form the junction (29). Thus, a process is provided for self-aligned fabrication of a Schottky junction having relatively low resistivity, wherein the shape and position of the junction can be well controlled.

Abstract: The present invention relates to a method for manufacturing an electronic assembly (50) comprising an electronic component, a cavity and a substrate which method comprises; —providing an electronic component (10) having a first pattern with a substantially closed configuration; —providing a cover (18) on a surface of the electronic component, which cover together with said surface defines a cavity (20), the closed configuration of the first pattern substantially enclosing the cover at said surface; —providing a substrate (30) having a second pattern with a substantially closed configuration, which closed configuration at least partially corresponds to the closed configuration of the first pattern and comprises a solder pad; —disposing solder material at the solder pad; —positioning the electronic component and the substrate so as to align both the substantially closed configurations of the first and second pattern, while the substrate supports a top surface (28) of the cover; —reflow-soldering the solder mate

Abstract: A frequency tunable arrangement (ICT) comprises a tunable oscillator circuit (TOC) that provides an oscillator signal (OS). A controllable frequency divider circuit (CDIV, DBT1, DBT2, DBT3, MUX) provides a frequency-divided signal (MO) on the basis of the oscillator signal. The frequency-divided signal has a frequency that is equal to the frequency of the oscillator signal divided by a division factor. The controllable frequency divider circuit provides any division factor among a set of division factors (4, 5, 6, 7, 8) in which for any division factor a ratio between that division factor and a lower division factor closest thereto, if existing, does not exceed 1.25.

Abstract: A method testing an SRAM having a plurality of memory cells is disclosed. In a first step, a bit value is written into a cell under test (CUT). Subsequently, the first and second enabling transistors are disabled and the bit lines are discharged to a low potential. Next, the word line (WL) coupled to the memory cell under test is activated for a predetermined period. During a first part of this period, one of the bit lines (BLB) is kept at the low potential to force the associated pull up transistor in the CUT into a conductive state, after which this bit line (BLB) is charged to a high potential. Upon completion of this period, the bit value of the first cell is determined. The method facilitates the detection of weak or faulty SRAM cells without requiring the inclusion of dedicated hardware for this purpose.

Abstract: Circuit arrangement, LIN comprising such circuit arrangement as well as method for processing input signals of the LIN In order to further develop a circuit arrangement (100)—for processing at least one input signal (12) from at least one data bus (10) of at least one LIN and—for providing the data bus (10) with at least one output signal (18), as well as a corresponding operating method in such way that EMI performance and/or EMI performance of the LIN (300) is improved, it is proposed to provide—at least one analog-digital converting circuit (ADC) for converting the analog input signal (12) into at least one digital signal (14) to be processed, and—at least one digital-analog converting circuit (DAC) for converting the processed digital signal (16) into the analog output signal (18).

Abstract: The present invention relates to an integrated Doherty type amplifier arrangement and an amplifying method for such an arrangement, wherein a lumped element hybrid power divider (12) is provided for splitting input signals of main and peak amplifier stages (20, 30, 40) at predetermined phase shifts and non-equal division rates and at least one wideband lumped element artificial line (Z 1, Z2) combined with wideband compensation circuit for receiving said first amplified signal and for applying said predetermined phase shift to said first amplified signal and its higher harmonics. Thereby, the low gain of the peak amplifier is compensated by providing the non-equal power splitting at the input. Moreover, the use of the lumped element hybrid power divider leads to an improved isolation between the input ports of the main and peak amplifiers decreasing final distortions of the output signal.

Abstract: An antenna switch (31) that is arranged to alternately operate in a receive mode and a transmit mode, comprises adaptive filter (30). Herewith, signal processing means (Rx1, Rx2 and Rx3) can be coupled to an antenna (1) during the receive mode and be insulated from the antenna during the transmit mode.

Abstract: The present invention relates to a method and circuit arrangement for determining power supply noise of a power distribution network. The power supply noise is determined by measuring the propagation delay of a delay circuit powered by the power distribution network, wherein the result of the measuring step is used as an indicator of the power supply noise. Thereby, a real-time power supply noise monitoring can be carried out at any point of a power distribution network of an observed circuitry.

Abstract: A data carrier (2) comprises a data circuit (4) arranged on a substrate (3) and data transmission unit (10) being connected to the data circuit (4). The data carrier (2) further comprises at least one strain gauge unit (7) being adapted to measure strains exerted on the substrate (3) and to transmit a deactivating signal (DE) to the data circuit (4) if the measured strains exceed a defined deactivating strain threshold. If the data circuit (4) receives the deactivating signal (DE), the data circuit (4) interrupts a data exchange with an external data reader/writer (1) via the data transmission unit (10).

Abstract: An electronic device is provided. The electronic device comprises at least one master network interface (MNI) with in a credit count unit (CC) for counting received credits and a first buffer unit (FIFO). The electronic device furthermore comprises at least one slave network interface (SNI) which comprises a threshold unit (TU) and at least one second buffer unit (FIFO). The electronic device furthermore comprises an interconnect (N) for coupling the at least one master network interface (MNI) and the at least one slave network interface (SNI). The slave network interface (SNI) is adapted to send a number of credits via the interconnect (N) to the master network interface (MNI) if the available amount of space or credits in the at least one second FIFO buffer (FIFO) reaches a threshold value stored in the threshold unit (TU).

Abstract: The invention relates to a field-effect transistor having a higher efficiency than the known field-effect transistors, in particular at higher operating frequencies. This is achieved by electrically connecting sources of a plurality of main current paths by means of a strap line (SL) being inductively coupled to a gate line (Gtl) and/or a drain line (Drnl) for forming an additional RF-return current path parallel to the RF-return current path in a semiconductor body (SB). The invention further relates to a field-effect transistor package, a power amplifier, a multi-stage power amplifier and a base station comprising such a field-effect transistor.

Abstract: A frequency selection device comprises an oscillator, which comprises a resonator mass which is connected by a spring arrangement to a substrate, and a piezoresistive element for controlling oscillation of the resonator mass, which comprises a piezoresistive element connected to the resonator mass. A current is driven through the piezoresistive element to control oscillation of the resonator mass. An input is provided for coupling a signal from which a desired frequency range is to be selected, to the resonator mass; and a detector is used for detecting a signal amplified by the oscillator.

Abstract: A method of active noise reduction is described which comprises receiving an audio signal (132) to be played, receiving a noise signal (105, 107, 116, 118, 126), indicative of ambient noise (111), from at least one microphone (104, 106), and generating a noise cancellation signal (114) depending on both, said audio signal (132) and said noise signal (105, 107, 116, 118, 126).

Abstract: A driving circuit for an opto-coupler comprising a switched mode regulator configured to convert a first voltage to a second voltage, the switched mode regulator operable in accordance with a control signal (311) representative of the first voltage, and wherein the second voltage is used to drive the diode (304a) of the opto-coupler (304), in use.

Abstract: The present invention relates to a detection circuit (100) capable to detect a rectified phase-cut or sinusoidal wave-form using its duty cycle or average value and in response, to select the respective dim mode amongst the linear phase-cut and step-dimming. The circuit (100) receives the rectified waveform with its duty cycle, which is derived through a comparator (22, 24) and converted into a DC signal. The latter which is controlled by the duty cycle is then compared to a reference level (40) through another comparator (20) that, in response, supplies a signal controlling a switching device (30). The switching device (30) will be thus automatically connected either to one set signal level when the DC signal is greater than the reference level (40), namely when the circuit (100) detects a rectified sinusoidal waveform, or to the same level as the DC signal when the DC signal is less than the reference level (40), namely when the circuit (100) detects a rectified phase-cut waveform.

Abstract: The invention relates to an apparatus 1 comprising a broadcast receiver circuit, an embedded antenna for receiving broadcast signals and a tuning circuit coupled between the antenna and the receiver circuit, which tuning circuit comprises a filter circuit coupled to ground, wherein the tuning circuit is designed to have a first resonance at a first frequency below a broadcast band of interest, and a second resonance at a second frequency above the broadcast band and wherein the tuning circuit comprises an amplifier with an output to the receiver circuit and with an input to the filter circuit, and wherein the tuning circuit is provided with a carrier to noise ratio (CNR) which is substantially fiat across the broadcast band.