Abstract: In summary, the invention relates to a device, a system, a method and a computer program for spectrum sensing. A detection procedure for detecting a signal of interest or an event by using a plurality of sensing devices capable of communicating with a central unit is proposed. The sensing devices can compute soft detection metrics and communicate this information to a central unit, where the information may be used to make a final detection decision using a certain specified rule. The signaling overhead of the proposed approach can be of the same order as that of a hard signaling approach. However, the proposed approach may achieve a better detection performance.

Abstract: An SRAM finFET cell includes fins (30 . . . 40) and respective insulated gates (62 . . . 72) forming finFET transistors, together with interconnects (86 . . . 92) connecting the fins and gates. The regions of the fins not covered by the insulated gates are doped. Each of the fins (30 . . . 40) extends in the same longitudinal direction; and each of the fins (30 . . . 40) is arranged laterally adjacent to another fin of the same conductivity type. The cell design reduces the effects of process spread.

Abstract: The invention relates to a current mirror circuit (40, 50, 60) comprising an input-side transistor (Q1) or field effect transistor and an output-side transistor (Q2) or field effect transistor, which are coupled with their emitters or sources and are connected to a voltage (UB, 55), which are electrically coupled with each other with their respective base (45, 46, 57, 58) or gate and are connected to a the field effect transistor (Q3) in such a way that the source (44) of the field effect transistor (Q3) is coupled to the base (45,46,57,58) or gate of the two transistors (Q1, Q2) or field effect transistors and the drain (47) of the field effect transistor (Q3) is coupled to the collector (48) or drain of the input-side transistor (Q1) or field effect transistor.

Abstract: Semiconductor dice (100, 200) of integrated circuit chips are provided with solder bump pads (130, 230) distributed over active areas of the dice to supply the I/O interconnects without including peripheral wire bond pads. The dice are further provided with protective ESD structures (140p/140i, 240p/240i) arranged in a network that includes ESD structures that extend into the interior areas of the dice. This allows the ESD structures to be placed proximate to respective power and ground connections, and positioned to reduce an average interconnect length between interior bump pads and the ESD structures relative to an average path length between the interior bump pads and the die peripheral area.

Abstract: Various exemplary embodiments relate to a High-Definition Multimedia Interface (HDMI) switch configured to receive notification of a switch from a current HDMI source to a new HDMI source, determine whether the new HDMI source is actively transmitting data, has attempted to access an HDCP register before a predetermined timeout delay since a last HDCP register access, and is transmitting unencrypted data, and based on these determinations, either immediately begin transmission of the HDMI data received from the new source or reset the new HDMI source. In this manner, various exemplary embodiments enable switching between HDMI sources with a reduced delay.

Abstract: An analog to digital conversion circuit comprises a first digital noise cancellation filter (16) configured to provide a signal to cancel quantization noise from an analog to digital converted output signal. In a calibration phase a second digital noise cancellation filter (26) is has an input coupled to an input of the first digital noise cancellation filter (16). Mutually different sets of at least one-filter coefficients are programmed in the first and second digital noise canceling filters (16, 26). A difference is computed of averaged size indications of digital output signals derived using signals from the first and second digital noise cancellation filters (16, 26) using the same input signal. Updates of the sets of at least one filter coefficients are adapted dependent on the difference between the averaged size indications.

Abstract: An apparatus for encoding video display data comprises a transmitter that is configured to accept an RGB data signal from a source and a receiver that is configured to accept the RGB data signal from the transmitter. The RGB data signal comprises redundant synchronization information. Methods of using the apparatus are also provided.

Abstract: Disclosed is a semiconductor device comprising a stack of patterned metal layers (12) separated by dielectric layers (14), said stack comprising a first conductive support structure (20) and a second conductive support structure (21) and a cavity (42) in which an inertial mass element (22) comprising at least one metal portion is conductively coupled to the first support structure and the second support structure by respective conductive connection portions (24), at least one of said conductive connection portions being designed to break upon the inertial mass element being exposed to an acceleration force exceeding a threshold defined by the dimensions of the conductive connection portions. A method of manufacturing such a semiconductor device is also disclosed.

Abstract: The present invention relates to a method for fabricating a planar independent-double-gate FET or a planar gate-all-around FET on a bulk semiconductor substrate. The method comprises refilling a surface recess in an active semiconductor region with a buried sacrificial layer, and, after preparing a pre-processing a gate stack by respective deposition and patterning, the formation of a recess in the isolation regions so as to cause the recess to extend, in a depth direction that points towards the inner substrate, to a depth level that allows removing the buried sacrificial layer and so as to cause the recess to undercut portions of gate stack in the channel direction.

Abstract: An electronic component (100, 1400) comprises a first electrode (106), a second electrode (107), a convertible structure (102) electrically coupled between the first electrode (106) and the second electrode (107), being convertible between at least two states by heating and having different electrical properties in different ones of the at least two states, and a retention enhancement structure (108, 1402) arranged between the first electrode (106) and the second electrode (107), connected to the convertible structure (102) and configured for suppressing conversion between different ones of the at least two states in the absence of heating.

Abstract: The present invention relates to a method and system (100) for ensuring a predetermined level of accuracy of a parallel orientation of a tool tip surface (112) with respect to a work piece holder (110) surface (108) of an assembly device. A grinding plate (130) is provided onto the work piece holder surface and a grinding material is deposited thereupon. The tool tip (106) is then moved to a predetermined distance above the grinding plate and moved relative to the grinding plate in a plane oriented substantially parallel to the grinding plate top surface (128). At a plurality of predetermined locations on the tool tip surface a distance between the tool tip surface and the work piece holder surface is measured and a level of accuracy of a parallel orientation of the tool tip surface with respect to the work piece holder surface is determined in dependence upon the measured distances.

Abstract: A method and system of fine timing synchronization for an OFDM signal. The OFDM signal is coarse timing synchronized, generating a synchronization sequence and a CFR (Channel Frequency Response). The synchronization sequence is removed. A correlation coefficient of the correlation between the CFR applied to a number of carriers and the number of carriers with different window shifts is calculated. The largest window shift corresponding to a downsampling factor is indicated by the lowest correlation coefficient greater than a threshold. The CFR is downsampled by the downsampling factor, and an inverse FFT is performed on the downsampled CFR with a reduced number of calculations reduced by the downsampling factor, transforming the CFR into a CIR. A fine timing synchronization position is determined from the CIR and is utilized by an FFT unit within an OFDM receiver to accurately receive OFDM symbols of the OFDM signal.

Abstract: A switching amplifier comprising: an output driving circuit (400) including a pair of switching transistors (M1, M2) connected in series between a pair of supply voltage lines (VP, gnd); a switch driver circuit (204a) configured to drive the switching transistors (M1, M2) with first and second respective PWM signals dependent on an input signal (101); an output connection between the pair of transistors (M1, M2) for driving an output load (403); and an output current sensing circuit for measuring a current through the output load, the output current sensing circuit comprising: a current sensing resistor (401a) connected between a first one (M2) of the pair of transistors and an adjacent supply voltage line (gnd); and a voltage sense circuit (404) connected across the current sensing resistor, wherein the voltage sense circuit is configured to sample a voltage across the current sensing resistor (401a) at a midpoint of successive corresponding portions of one of the PWM signals.

Abstract: The present invention relates to a manufacturing method of an integrated circuit (IC) comprising a substrate (10) comprising a pixelated element (12) and a light path (38) to the pixelated element (12). The IC comprises a first dielectric layer (14) covering the substrate (10) but not the pixilated element (12), a first metal layer (16) covering a part of the first dielectric layer (14), a second dielectric layer (18) covering a further part of first dielectric layer (14), a second metal layer (20) covering a part of the second dielectric layer (18) and extending over the pixelated element (12) and a part of the first metal layer (16), the first metal layer (16) and the second metal layer (20) forming an air-filled light path (38) to the pixelated element (12).

Abstract: A mobile communication device (1) comprises a MIFARE memory (MM) being configured as a MIFARE Classic card or an emulated MIFARE Classic memory and a MIFARE application manager (MAM) being adapted to install MIFARE applications in the MIFARE memory (MM). When a MIFARE application (MA) is a multiple sector application being too large to be stored in one sector of the MIFARE memory (MM) the MIFARE application manager (MAM) splits said multiple sector MIFARE application (MA) in parts (TK81-1, TK8-2, TK8-3) each being small enough for being stored in one sector of the MIFARE memory (MM), installs the parts (TK81-1, TK8-2, TK8-3) of the multiple sector MIFARE application (MA) in free sectors of the MIFARE memory (MM) and stores in the MIFARE memory (MM) an indication in which sectors the parts (TK81-1, TK8-2, TK8-3) of the multiple sector MIFARE application (MA) are located.

Abstract: An analog-to-digital converter comprises a signal input (6) for receiving an analog input signal and a set of comparators (4). Each comparator (4) has a first input (21) connected to the signal input (6) and a second input (22) connected to a reference voltage (16). Each comparator generates an output based on the comparison of the signals at the first input (21) and second input (22). The reference voltage is the same for all comparators. The set of comparators (4) has a non-identical response to the reference voltage (16) and the input signal and is due to an internally arising offset. An adder (25) determines a sum of the outputs of the set of comparators and conversion logic (27) generates an output digital signal dependent on the determined sum. Multiple sets of comparators can be provided, each set having a different respective reference voltage.

Abstract: A small hardware implementation is provided for the Advanced Encryption Standard SubByte function that implements the affine transform and inverse transform in a single Affine-All transform using a multiplicative inverse ROM. The logic is greatly reduced and the maximum path delay is reduced compared to a multiplexor implementation and is slightly greater than a ROM implementation.

Abstract: A current limiting circuit, especially for an RF power amplifier (PA) having a power control loop. The circuit is adapted to sense a representation of a bias current fed to a final stage of the PA. The sensed representation of the bias current is compared to a predetermined reference current and a signal is fed back to the power control loop upon the sensed representation of the bias current exceeding the reference current so as to limit output current of the PA. This provides a limitation of a current drawn by the PA which is generally insensitive to supply voltage and temperature variations. Optionally, a second circuit may be added to limit current drawn by the PA. The second circuit comprising a high accuracy VI converter that is adapted to compare a voltage VLIM representing a feed-back voltage of the power control loop and a predetermined reference voltage VBGAP.

Abstract: The invention provides for a method and apparatus for writing data to an optical disc and comprising recovering an output signal from optical reading head, scaling the said output signal responsive to secondary data derived from the disc by way of the optical reading head and deriving a Land Pre Pits (LPP) signal for use during recording to the disc from the said scaled output signal wherein the said scaling is arranged to increase the LPP signal when the LPP is identified as located adjacent a mark on the disc of low light reflectivity.

Abstract: Arrangement for accepting an input signal in a first voltage range and producing an output signal in a second voltage range. A transition detection circuit (230) detects a transition from a high level to a low level of the input signal and a control circuit (245) operates a first FET to produce the low level of the output signal. A second FET is operated by the high level of the input signal to output the high level of the output signal.