Abstract: A switched mode power converter is provided which includes a transformer (2) having a primary winding (2a) and at least one secondary winding (2b); a primary side active switch device (S1) coupled to the primary winding for selectively applying an input voltage to the primary winding; and a secondary side rectifier circuit including an output filter (6, 12) coupled to the at least one secondary winding (2), and first and second active switch devices (16, 14) coupled between the at least one secondary winding (2b) and the output filter. The switch devices are arranged such that each one is operable independently of the other to block current between the at least one secondary winding and the output filter in an opposite direction to the other. This facilitates better regulation of the converter and avoids the occurrence of voltage spikes encountered in existing configurations.

Abstract: The present invention relates to a data pipeline management system and more particularly to a minimum memory solution for unidirectional data pipeline management in a situation where both the Producer and Consumer need asynchronous access to the pipeline, data is non-atomic, and only the last complete (and validated) received message is relevant and once a data read from/write to the pipeline is initiated, that data must be completely processed. The data pipeline management system according to the invention can be implemented as a circular queue of as little as three entries and an additional handshake mechanism, implemented as a set of indices that can fit in a minimum of six bits (2×2+2×1). Both the Producer and Consumer will have a 2 bit index indicating where they are in the queue, and a 1 bit binary value indicating a special situation. Both parties can read all the indices but can only write their own, i.e. P and wrapP for the Producer and C and wrapC for the Consumer.

Abstract: An apparatus and method for generating a shared secret between at least two wireless portable electronic devices. A shared secret is generated by holding together the at least two devices and shaking them. An acceleration of the at least two devices is measured at least during a time window beginning at a time corresponding to when a magnitude of the acceleration exceeds a predetermined threshold. The acceleration is sampled, resulting in a plurality of vectors, such that a first vector is an initial sample of the acceleration during the time window. In some embodiments, the acceleration is measured in three dimensions. Dot products are calculated between the first vector and each of a plurality of subsequent vectors, resulting in an array of scalars. At least a portion of this array is used to generate the shared secret between the at least two devices.

Abstract: An power stage has a differential output stage 2 driven by one or more buffer stages 4. The buffer stages 4 are implemented as high and low side buffers 12,14, each of which is itself a differential buffer implemented using transistors formed in an isolated-well technology such as triple-well CMOS.

Abstract: The invention relates to a method for selective deposition of Si or SiGe on a Si or SiGe surface. The method exploits differences in physico-chemical surface behaviour according to a difference in doping of first and second surface regions. By providing at least one first surface region with a Boron doping of a suitable concentration range and exposing the substrate surface to a cleaning and passivating ambient atmosphere in a prebake step at a temperature lower or equal than 800° C., a subsequent deposition step of Si or SiGe will not lead to a layer deposition in the first surface region. This effect is used for selective deposition of Si or SiGe in the second surface region, which is not doped with Boron in the suitable concentration range, or doped with another dopant, or not doped. The method thus saves a usual photolithography sequence required for selective deposition of Si or SiGe in the second surface region according to the prior art.

Abstract: A lighting unit comprises a packaging substrate (10) formed from a semiconductor, a channel (12) formed in the substrate and a discrete light emitting diode arrangement (34) in the channel. A surface region of the channel comprises doped semiconductor layers (20,24) which define a light sensor. The arrangement provides a light sensor (which can be used to determine colour and/or output flux) for a LED unit, with the light sensor embedded in substrate used for packaging. This provides a low cost integration process and provides good registration between the light sensor and the LED output.

Abstract: A method and system determines an absolute Multicast-Broadcast Single Frequency Network (MBSFN) configuration based on a threshold. First saved radio resources and first wasted radio resources are calculated. The absolute MBSFN configuration is set as the final MBSFN configuration when the first saved radio resources are greater than or equal to the first wasted radio resources. When untrue, the absolute MBSFN configuration plus an adjacent cell pool is set as the final MBSFN configuration based on the final MBSFN configuration achieving a maximum value of second saved radio resources minus second wasted radio resources. When both of these conditions are untrue, the absolute MBSFN configuration minus an MBSFN cell pool is set as the final MBSFN configuration based on the final MBSFN configuration achieving a maximum value of third saved radio resources minus third wasted radio resources.

Abstract: A read only memory is manufactured with a plurality of transistors (4) on a semiconductor substrate (2). A low-k dielectric (10) and interconnects (14) are provided over the transistors (4). To program the read only memory, the low-k dielectric is implanted with ions (22) in unmasked regions (20) leaving the dielectric unimplanted in masked regions (18). The memory thus formed is difficult to reverse engineer.

Abstract: A coarse integer carrier frequency offset CFO compensator (138) for an orthogonal frequency division multiplexor OFDM receiver. The coarse integer CFO compensator includes a subcarrier grouping engine (146), a signal power calculator (148), and a search range identifier (150). The subcarrier grouping engine groups a plurality of subcarriers into two groups based on a coarse acquisition range parameter, Q, corresponding to a coarse acquisition range. The signal power calculator identifies a coarse estimate of an integer CFO based on a computed maximum value of a signal power function. The signal power function is based on a constructed sequence of the plurality of subcarriers. The search range generator identifies a fine acquisition range. The fine acquisition range is narrower than the coarse acquisition range.

Abstract: The invention relates to an integrated circuit card (1) comprising: an input/output block (4) for receiving external command data from an interface device (2); a central processing unit (CPU) (3) in signal communication with the input/output block (4) for performing a task corresponding to the received command data; a judgement block (5) in signal communication with the central processing unit (3) for judging whether a working time of the central processing unit (3) reaches a reference time, after an input of the external command data is completed; and a control block (6) in signal communication with the judgement block (5) for operating responsive to an output of the judgement block, wherein the control block controls such that a S(WTX request) is output via the input/output block (4) without intervention by the central processing unit whenever the interface device (2) connected to the integrated circuit card (1) transmits a command to the integrated circuit card and the integrated circuit card is not able t

Abstract: Input/Output (I/O) pin circuits, devices, methods and systems are implemented in various fashions. According to one such method, a valid signal level is provided for a pin of an integrated circuit (IC) die. Responsive to a reset signal, a first mode (304) is entered where one of a pull-up circuit or pull-down circuit is enabled (308, 310) to set the pin to the valid signal level. A change in signal level of the pin that is a deviation from the valid signal level is detected (312). Responsive to detecting the change, a second mode (314) is entered where the one of a pull-up circuit or pull-down circuit is disabled (316).

Abstract: A class H amplifier circuit includes a Buck converter 20 and a charge pump 30 which are used to generate voltages which are used in turn to power an output driver 10. A feedback path 36 controls the loop. The circuit is particularly suitable as a high efficiency circuit for driving headphones or loudspeakers.

Abstract: An overload protection circuit and method for a fluorescent lamp drive circuit is presented, the fluorescent lamp drive circuit having first and second switches connected in series and a controller adapted to switch the switches on and off alternately. The overload protection circuit is adapted to detect a voltage across the first switch, and to turn off the first switch based on whether the detected voltage exceeds a first threshold voltage.

Abstract: The present invention relates to a method for fabricating a FinFET on a substrate. The method comprises providing a substrate with an active semiconductor layer on an insulator layer, and concurrently fabricating trench isolation regions in the active semiconductor layer for electrically isolating different active regions in the active semiconductor layer from each other, and trench gate-isolation regions in the active semiconductor layer for electrically isolating at least one gate region of the FinFET in the active semiconductor layer from a fin-shaped channel region of the FinFET in the active semiconductor layer.

Abstract: The invention relates to a CMOS input circuit for receiving low-swing input signals, which is an alternative to the CMOS input circuits as known from the prior art.

Abstract: Magnetic shield layout (10, 10 A-10 G) arranged for an integrated circuit of a semiconductor device comprising at least a first inductor (1) having a first crosssectional inductor-area (11), and at least a second inductor (2) having a second crosssectional inductor-area (12), wherein the inductor-areas (11, 12) are located in an inductor-plane (P) and wherein the first and second inductors (1, 2) in operation are subject to an induction coupling; at least one magnetic shield (20) for reducing the induction coupling, said magnetic shield having a conductive path (21) marking a first crosssectional shield-area (13) assigned to the first cross-sectional inductor-area (11) and a second crosssectional shield-area (14) assigned to the second crosssectional inductor-area (12); wherein the shield-areas (13, 14) are conductively and continuously connected by the conductive path (21) such that in operation a magnetic field generated by the first inductor (1) is largely cancelled by the magnetic field of the second cros

Abstract: A method of testing an integrated circuit, comprises providing a test vector to a shift register arrangement by providing test vector bits in series into the shift register arrangement (20) timed with a first, scan, clock signal (42). The test vector bits are passed between adjacent portions of the shift register arrangement timed with the first clock signal (42) and an output response of the integrated circuit to the test vector is provided and analyzed. The output response of the integrated circuit to the test vector is provided under the control of a second clock signal (56) which is slower than the first clock signal. This testing method speeds up the process by increasing the speed of shifting test vectors and results into and out of the shift register, but without comprising the stability of the testing process. Furthermore, the method can be implemented without requiring additional complexity of the testing circuitry to be integrated onto the circuit substrate.

Abstract: A method for determining the centroid of a wafer target. In one embodiment, the method comprises a series of steps in a stepper, starting with the step of receiving a wafer, having a target set formed therein. Next, a signal is passed over the target set and over a material separating target shapes in the target set. Then a return signal is reflected, and received, from the surface of the target shapes and the material separating them. A location of at least one maxima point of the return signal is identified. Finally, a centroid is determined as the median of the locations of at least one maxima point.

Abstract: The invention relates to a method of manufacturing a semiconductor device comprising a field effect transistor, in which method a semiconductor body of silicon with a substrate is provided at a surface thereof with a source region and a drain region of a first conductivity type which are situated above a buried isolation region and with a channel region, between the source and drain regions, of a second conductivity type, opposite to the first conductivity type, and with a gate region separated from the surface of the semiconductor body by a gate dielectric and situated above the channel region, wherein a mesa is formed in the semiconductor body in which the channel region is formed and wherein the source and drain regions are formed on both sides of the mesa in a semiconductor region that is formed using epitaxial growth, the source and drain regions thereby contacting the channel region.

Abstract: A method of forming an interconnect structure, comprising forming a first interconnect layer (123) embedded in a first dielectric layer (118), forming a dielectric tantalum nitride barrier (150) by means of atomic layer deposition on the surface of the first interconnect (123), depositing a second dielectric layer (134) over the first interconnect (123) and the barrier (150) and etching a via (154) in the dielectric layer (134) to the barrier (150). The barrier (150) is then exposed to a treatment through the via (154) to change it from the dielectric phase to the conductive phase (180) and the via (154) is subsequently filled with conductive material (123).