Abstract: A Trench gate MOS field-effect transistor having a narrow, lightly doped, region extending from a channel accommodating region (3) of same conductivity type immediately adjacent the trench sidewall. The narrow region may be self-aligned to the top of a lower polysilicon shield region in the trench or may extend the complete depth of the trench. The narrow region advantageously relaxes the manufacturing tolerances, which otherwise require close alignment of the upper polysilicon trench gate to the body-drain junction.

Abstract: A wireless receiver is activated periodically to measure the level of received signals. It measures the average received level over a plurality of the activation periods, and enables the supply of power to receiver circuitry dependent on the measured average value. In one embodiment the power is enabled if an increase in the average value is detected which is greater than a predetermined margin. The average value may be measured in a sliding or stepped window. In another embodiment the power is enabled if the level in an activation period exceeds the average value by a predetermined margin.

Abstract: In a method of determining the distance (d) between an integrated circuit (1) and a substrate (2) emitted light enters the at least semi transparent substrate (2), passes through the substrate (2) and an at least semi transparent material (8), is reflected by the integrated circuit (1), passes again through the material (8) and the substrate (2), and leaves the substrate (2). The at least semi transparent material (8), particularly is an at least semi transparent adhesive, provided between the substrate (2) and the integrated circuit (1). The distance (d) between the substrate (2) and the integrated circuit (1) is determined by evaluating the intensities of the light leaving and entering the substrate (2), particularly by evaluating the ratio between the intensities of the light leaving and entering the substrate (2).

Abstract: Magnetoresistive sensors are commonly used for angular detection in many automotive applications. According to an exemplary embodiment of the present invention, a sensor is provided in which a first half-bridge has magnetoresistive resistors with barber-pole stripes and in which a second half-bridge has magnetoresistive resistors without barber-pole stripes. One of the resistors without barber-pole stripes is rotated with respect to the other three resistors by 90°. This may provide for an improved angle determination with reduced angular errors due to offset.

Abstract: A magnetic field sensor assembly (401a, 401b) for measuring an angular direction (?) of a sensed magnetic field (Happl) relative to the assembly, the sensor assembly comprising: a sensor (404a, 404b) of a first type configured to sense an orientation of the sensed magnetic field; a sensor (402, 406) of a second type configured to measure an orientation and a direction of the sensed magnetic field; and processing circuitry (403, 405) connected to each of the magnetic field sensors, the processing circuitry being configured to process output signals from the sensor of the first type to determine an uncorrected sensed magnetic field angle and to apply an offset angle to the uncorrected magnetic field angle dependent on a logical combination of signs of output signals from the sensors of the first and second types.

Abstract: A program is obfuscated by reordering its instructions. Original instruction addresses are mapped to target addresses in an irregular way, with position dependent address steps between the addresses of logically successive instructions. Preferably pseudo-random address steps are used, for example with address steps that have mutually opposite sign with equal frequency. The data processing device has an instruction flow control unit that updates instruction addresses according the position dependent address steps. The instruction flow control unit may comprise a circuit that contains secret information, which is not normally accessible from the outside, to control the updates. A lookup table may be used for example, with address steps, successor addresses or mapped address values. In an embodiment the mapping of original instruction addresses to target addresses may be visualized by means of a path (36) along points in an n-dimensional array, where n is greater than one.

Abstract: A circuit configuration for obtaining a binary output signal from a current signal delivered by a magnetic-field sensor comprises a magnetic-field sensor (1), which is supplied at two terminals (2; 3) with a supply voltage and which delivers from these terminals (2; 3) a current signal essentially alternating in pulse shape between two current values, a voltage-supply unit (50) to supply the magnetic-field sensor (1) with a stabilized supply voltage, a measuring device (51) for tapping the pulse-shaped current signal from the magnetic-field sensor (1) and for delivering a measuring signal, a signal-conditioning stage (52) for forming an analogue voltage signal from the measuring signal, an analogue/digital converter stage (6) for obtaining a digital voltage signal from the analogue voltage signal, a control stage (7) for obtaining a first and a second signal value from the digital voltage signal, wherein the signal values represent the two current values of the current signal, alternating in pulse shape, as s

Abstract: A method of manufacturing a semiconductor device (1200), the method comprising forming a sacrificial pattern having a recess on a substrate (402), filling the recess and covering the substrate and the sacrificial pattern with a semiconductor structure, forming an annular trench in the semiconductor structure to expose a portion of the sacrificial pattern and to separate material (904) of the semiconductor structure enclosed by the annular trench from material (906) of the semiconductor structure surrounding the annular trench, removing the exposed sacrificial pattern to expose material of the semiconductor structure filling the recess, and converting the exposed material of the semiconductor structure filling the recess into electrically insulting material (1202).

Abstract: The time slot index for wireless signals is synchronized using an approach that facilitates rapid synchronization acquisition and tracking synchronization recovery. According to an example embodiment, a synchronization circuit (e.g., 300) uses data in symbols of a particular signal frame (e.g., 120) to set a time slot index synchronization characteristic for an acquired wireless signal, and further to track time slot index synchronization during processing of the signal.

Abstract: A technique for managing uplink feedback involves establishing a channel quality threshold range, for example, in terms of a channel quality indicator (CQI), broadcasting the channel quality threshold range to the mobile stations and using the channel quality threshold range to control the feedback of channel quality information. For example, the mobile stations determine their own mobile station-specific CQI and then generate CQI feedback information in response to a comparison between their own mobile station-specific CQI and the CQI threshold range. In an embodiment, if the CQI of a mobile station falls within the CQI threshold range, then the mobile station can transmit a reduced set of CQI feedback information. For example, the reduced set of CQI feedback information may be a single bit that indicates whether the mobile station-specific CQI is greater than or less than a CQI threshold or whether the CQI has crossed a CQI threshold.

Abstract: Mixer-systems comprising gain-blocks (1-4) and switches (5-8) have a flexibility depending upon their configuration (insight) and are made more flexible (basic idea) by supplying data input signals to the gain-blocks (1-4) and oscillation signals to the switches (5-6) for switching couplings between the gain-blocks (1-4). A switch (5-6) comprises a switch-transistor and a gain-block (1-4) either comprises a gain-block-transistor or comprises five gain-block-transistors for increasing the linearity of the mixer-system. The switches (5-6) have main electrodes which in the balanced situation are all coupled via four impedances (13-16) to the gain-blocks (1-4). In the single ended situation two main electrodes are coupled via two impedances (13,15,18,20) to the gain-blocks (1-4) and two others are coupled directly to the gain-blocks (1-4). By introducing further switches (7-8) parallel to the switches (5-6), harmonics can be suppressed.

Abstract: A signal level adjusting device (AD), for RF communication equipment arranged to received primary RF signals, comprises i) a tuner (TU) comprising a gain control means (SI,R), arranged to define a first or second digital command signal respectively each time it receives a first or second digital control signal respectively, and a gain adjusting means (VGA) arranged to decrease or increase respectively its gain by a fixed value when the command signal defined by the gain control means (SI,R) is a first or second command signal respectively, in order to adjust the level of the received primary RF signals, and ii) a demodulator (DEM) comprising a level control means (LCM1) arranged to generate a first or second digital control signal respectively each time it detects an increase or decrease respectively of the level of secondary signals representative of the adjusted signals output by the tuner (TU).

Abstract: A 3-way Doherty amplifier has an amplifier input and an amplifier output. The amplifier has a main stage, a first peak stage and a second peak stage. The amplifier has an input network connecting the amplifier input to the inputs of the stages, and an output network connecting the stages to the amplifier output. The output network implements a phase shift of 90° between the output of the main stage and the amplifier output; a phase shift of 180° between the output of the first peak stage and the amplifier output; and a phase shift of 90° between the third output and the amplifier output.

Abstract: The invention relates to a semiconductor device comprising a test structure (100) for detecting variations in the structure of the semiconductor device, the test structure (100) comprising a first supply rail (110), a second supply rail (120), a ring oscillator (130) coupled between the first supply rail (110) and second supply rail (120), the ring oscillator (130) having an output (132) for providing a test result signal, and an array (140) of individually controllable transistors (142) coupled in parallel between the first supply rail (110) and the ring oscillator (130). Variations in the current output of the respective transistors (142) in the array (140) lead to variations in the respective output frequencies of the ring oscillator (130). This gives a qualitative indication of the aforementioned structural variations.

Abstract: Multi-lane PCI express busses devices, methods and systems are implemented in various fashions. According to one such implementation, a method is used for synchronizing data transfers between IC dies of a plurality of integrated-circuits (IC) dies. In a first IC die, a synchronizing signal is received and latched in a first clock domain and in the first IC die to produce a first latched output signal. The latched output signal is provided for use by each of the plurality of IC dies. In each of the plurality of IC dies, the first latched output signal is latched in the first clock domain to produce a second latched output signal. The second latched output signal is latched in a second clock domain to produce a third latched output signal. The third latched output signal is used to synchronize a respective communication lane.

Abstract: The present invention relates to a FinFET with separate gates and to a method for fabricating the same. A dielectric gate-separation layer between first and second gate electrodes has an extension in a direction pointing from a first to a second gate layer that is smaller than a lateral extension of the fin between its opposite lateral faces. This structure corresponds with a processing method that starts from a covered basic FinFET structure with a continuous first gate layer, and proceeds to remove parts of the first gate layer and of a first gate-isolation layer through a contact opening to the gate layer. Subsequently, a replacement gate-isolation layer that at the same time forms the gate separation layer fabricated, followed by filling the tunnel with a replacement gate layer and a metal filling.

Abstract: A driver circuit (10) for a light emitting diode comprises a first driver circuit (32, 32?, 32?) for generating a first current output for driving the light emitting diode, wherein the first driver circuit has a control switch for interrupting the supply of the first current output. A second driver circuit (50) is for generating a second current output for driving the light emitting diode, and the second driver circuit also has a control switch for interrupting the supply of the second current output. The overall output of the driver circuit comprises a pulse width modulated output current which alternates between a high current (Ihigh) generated by the first driver circuit and a low current (Ilow) generated by the second driver circuit. By providing separate driver circuits for two different current requirements, the circuits can be optimised for each function. For example the high current value can comprise an LED operation current, and the low current value can comprise a non-zero measurement current.

Abstract: The invention relates to a method of synchronising the clock of different clusters including a first cluster (1) and a second cluster (2) which are connected by means of a connecting element (3) wherein the timing of the second cluster (2) is at least almost aligned to the timing of the first cluster (1), wherein the timing of the second cluster is determined by a node (4) of the second cluster which is connected to a reference node of the first cluster and wherein the node of the second cluster synchronises itself with the reference node's timing and transfers an offset correction to the second cluster.

Abstract: The invention provides a method for regulating a LED current (ILED) flowing through a LED circuit arrangement at a mean LED current level. The method includes establishing an oscillating converter current(IL), establishing a first and a second current control indicator representative of a flow of a converter current (IL); regulating a peak and valley current level of the converter current in dependence on the first current control indicator; controlling a converter current period (T) of an oscillation of the converter current in dependence on the second current control indicator to be within a period control range (Tref) and feeding at least part of the converter current to the LED circuit arrangement. The invention also provides a circuit arrangement for regulating a LED current using the method, a LED driver IC using the circuit arrangement, a circuit composition with at least one LED and the circuit arrangement, and a lighting system with the circuit composition.

Abstract: An integrated circuit has a matrix of rows and columns of cells (10, 18, 19), each cell (10, 18, 19) comprising a first inverter (100) and a second inverter (102). First columns have a bit-line (12a,b), the first inverter (100) and the second inverter (102) in each cell of the first columns being cross-coupled to each other and coupled to bit-line (12a,b) of the associated first column. A further column is provided in the matrix with bit line fragments (16) that are mutually disconnected. Delays are monitored by coupling at least the first inverters (100) of cells in respective pairs of rows in series via the bit-line fragments and measuring a delay during signal propagation through the series connection, for example by in corporating the series of inverters in a ring oscillator.