Abstract: The present invention relates to a method and device for monitoring a lithographic process of an integrated circuit. In a first step a design for an integrated circuit is provided. The integrated circuit comprises at least an integrated circuit transistor pair having a gate of a first transistor connected to a gate of a second transistor. The gate of the second transistor is designed such that it has a predetermined overlap with respect to a source and a drain of the second transistor. A detection circuit is connected to the at least an integrated circuit transistor pair for detecting if in operation functionality of the second transistor of each of the at least an integrated circuit transistor pair is one of a transistor and a short circuit. The integrated circuit is then manufactured in dependence upon the desogn. After manufacturing, the detection circuit is used to determine the functionality of the second transistor of each of the at least an integrated circuit transistor pair.

Abstract: A device processes signals from a plurality of signal channels that are received in parallel. A channel processing circuit (12a,b, 14a,b), applies a series of filtering operations selectively to the signal from a first one of the signal channels. A filter management circuit (18) detects a reception condition from reception of a signal in a second one of the signal channels. The filter management circuit (18) controls application of at least a part of said filtering operations to the signal from the first one the signal channels by the channel processing circuit (12a,b, 14a,b), dependent on the detected reception condition. Selected filter operations may be enabled or disabled. Thus, power consumption may be reduced. In an embodiment, the detected reception condition is determined as a by-product of functional reception of another channel. Thus power consumption for the detection of the reception condition is also reduced.

Abstract: A power island for a system-on-a-chip (SoC) includes a first segment, a second segment, and a supply line. The first segment includes a hardware device and operates the hardware device at first power characteristics indicative of at least a first voltage. The second segment includes scalable logic and operates the scalable logic at second power characteristics indicative of at least a second voltage. The second power characteristics of the scalable logic are different from the first power characteristics of the hardware device. The supply line receives an external supply signal (VDD) and directs the external supply signal to both the first segment and the second segment. The second segment changes at least one power characteristic of the external supply signal to operate the scalable logic according to the second power characteristics.

Abstract: The present invention relates to a memory cell with a memory capacitor (110) on an active semiconductor region (104), the memory capacitor having a first capacitor-electrode layer, which, in a cross-sectional view of the memory cell, has first (218.1) and second (218.2) electrode-layer sections that extend on the active semiconductor region in parallel to the surface of the active semiconductor region at a vertical distance to each other and that are electrically connected by a third electrode-layer section extending vertically, that is, perpendicular to the surface of the active semiconductor region. A control transistor (112) is connected with a conductive second capacitor electrode layer that extends between the first and second electrode-layer sections and is electrically isolated from them by an isolation layer (116). Achieved advantages comprise a high manufacturing yield can, reduced fabrication cost and reduced risk of junction leakage by a small area required for the memory cell.

Abstract: A method of determining the dominant output wavelength of an LED, comprises determining an electrical characteristic of the LED which is dependent on the voltage-capacitance characteristics, and analysing the characteristic to determine the dominant output wavelength.

Abstract: The present invention relates to a clock supervision unit (100) and an electronic system clocked by at least one clock (c*) and using the clock supervision unit (100). The clock supervision unit (100) analyzes the at least one clock (c*) based on a monitor clock (m*) provided together with the at least one clock (c*) or separately to the clock supervision unit (100). The clock supervision unit (100) at least comprises an activity unit (210), a deviation unit (220) and an auxiliary clock generator (240). The auxiliary clock generator (240) outputs an auxiliary clock (a*). The activity unit (210) detects the presence of the monitor clock (m*) based on the auxiliary clock (a*) and the presence of the auxiliary clock (a*) based on the monitor clock (m*). The deviation unit (220) detects clock faults in the monitor clock (m*) based on the auxiliary clock (a*).

Abstract: A method and an apparatus for organizing media files in a database. Embodiments of the present invention provides a method to associate artwork to a media file. A plurality of first data artwork images is provided. A plurality of second data is generated based on the first data, each second data identifiers for the artwork images corresponding to a different first data of the plurality of first data. A plurality of third data media files is provided and each third data has at least one attribute and a reference field for storing a corresponding second data. Each third data is identified in the database by the at least one attribute and the reference field. And, a plurality of fourth data album titles each associated with a subset of the plurality of third data is provided.

Abstract: Wireless communications devices, methods and systems are implemented in various fashions. According to one such implementation, a method is used in a device using time-division-multiple access and multiple-mode wireless modules. Logic generates a signal indicative (304) of a first (e.g., TV) wireless module (150) being active. In a first state where the first wireless module (150) is active, a switch connects a transmitter of a second (e.g., cellular) wireless module (100) to a duplexer (202). In a second state where the first wireless module is not active, logic connects the transmitter of the second wireless module (100) to an antenna (102) while bypassing the duplexer (202). Logic connects, in the first state, the duplexer (202) to the antenna (102) and connects, in the second state, the transmitter to the antenna while bypassing the duplexer (202).

Abstract: The present invention relates to an analog memory circuit, i.e. a sample and hold circuit, wherein the source and the gate of the switching transistor is maintained at a same potential prior and after the sampling process using a transistor circuitry. The analog memory circuit comprises a memory capacitor (102) connected at a first end to a first port (104), which is connected a reference potential (106). A drain of a first transistor (108) —switch transistor—is connected to a second end of the memory capacitor (102). A source of the first transistor (108) is connected to a second port (110), which is connected to circuitry (112) for providing an input signal for storage in the memory capacitor (102), and a gate of the first transistor (108) is connected to a third port (114), which is connected to a first current sink (116).

Abstract: In a method of determining the distance (d) between an integrated circuit (1) and a substrate (2) a picture (31,32) of the integrated circuit (1) is taken. The integrated circuit (1) is attached to the substrate (2) that is at least semi transparent. An at least semi transparent material, particularly an at least semi transparent adhesive (8), is located between the integrated circuit (1) and the substrate (2). The picture (31,32) of the integrated circuit (1) is taken through the substrate (2) and the material (8). The picture (31,32) and/or image data related to the picture (31,32) is evaluated and the distance (d) between the integrated circuit (1) and the substrate (2) is determined in response to the evaluated picture (31,32) and/or image data related to the picture (31,32).

Abstract: A message memory (1) with a flexible association between the message-object memories of the message memory (2) and the segments of a physical memory (3). The association is made through configuration, wherein one or more memory segments form a cluster as a function of the length of the message content to be stored.

Abstract: A wireless terminal includes a housing (10) containing a substrate (12) having a ground plane, RF components mounted on the substrate, a PIFA (Planar Inverted-F Antenna) (16) carried by the substrate and coupled electrically to the RF components for transmitting and receiving signals and a notch antenna (14) in the substrate for receiving signals in a frequency band at least partially overlapping the transmission bandwidth of some of the signals transmitted by the PIFA. The notch antenna is de-activated when the PIFA (16) is being used for transmitting a signal lying within the said transmission bandwidth.

Abstract: A time-triggered communication system in a dual-channel network of singlechannel architecture, wherein in each case one communication controller (2, 6) is assigned to one channel, and two corresponding communication controllers (2, 6) communicate with one another via an inter-channel interface (1a, 1b). Said inter-channel communication contains information about limiting points (G1, G2 . . . G12) of a time path. A limiting point (G1, G2 . . . G12) is, for example, the point in time when a cycle starts. The interchange of limiting points enables the temporal offset of the two channels to be determined as well as a correction value. After every two cycles also the rate error of the local clocks can be ascertained and a suitable correction value determined. The reliability of safety-relevant networks is increased by the time-triggered communication system described hereinabove.

Abstract: The invention relates to a MEMS resonator comprising a movable element (48), the movable element (48) comprising a first part (A) having a first Young's modulus and a first temperature coefficient of the first Young's modulus, and the movable element (48) further comprising a second part (B) having a second Young's modulus and a second temperature coefficient of the second.

Abstract: The present invention relates to a double data rate interface and method for use between a processor and random access memory, comprising a delay line including means for creating a delay in a data strobe signal from the random access memory, the delay line being arranged such that the delay in the data strobe signal is equal to the sum of set-up time and data bus rise time. The interface of includes the delay line comprising the delay locked loop which in turn comprises a ring oscillator. The ring oscillator includes a buffer and a Vernier delay.

Abstract: A demodulator circuit (DMOD) for amplitude-modulated signals is defined which comprises a threshold switch module (SWS), wherein a signal output (SA) of the threshold switch module (SWS) is connected to the output (DA) of the demodulator circuit (DMOD) and a signal input (SE) of the threshold switch module (SWS) is connected via a first capacitor (C1) to the input (E) of the demodulator circuit (DMOD). In addition, the signal input (SE) can be connected via a coupling element (KO) to a first or alternatively a second.

Abstract: In a method of auto-tuning a radio FM-receiver the receiver frequency band is scanned until a FM signal is received meeting criteria for identifying the signal as being of a predetermined quality, particularly coming from a valid FM station. At least during tuning it is permanently established whether or nor the FM signal meets the criteria, whereafter the results thereof are read a predetermined number of times, and the FM signal is only stored if at least most of these times the criteria are met. Particularly, the results are read 10 times and the FM signal is only stored if at least 8 times thereof the criteria are met.

Abstract: A Multi-carrier Switch Converter (“MCSC”) for multiplexing a plurality of input signals received at the MCSC into a single MCSC output signal is disclosed. The MCSC may include a Multi-port Selector Switch, wherein the Multi-port Selector Switch receives the plurality of input signals and produces a Multi-port Selector Switch output, wherein the Multi-port Selector Switch output includes a plurality of switched output signals and a frequency translation block in signal communication with the Multi-port Selector Switch, wherein the frequency translation block receives the Multi-port Selector Switch output and frequency translates each switched output signal of the plurality of switched output signals to plurality of translated signals, wherein each translated signal has a fixed carrier frequency.

Abstract: A method of transcoding a content stored on a first server (OS) is provided. The first server (OS) is arranged within an UPnP network comprising at least one first server (OS), at least one UPnP renderer (UR) and at least one UPnP control point (CP). The content directoryservices (CDS) of the at least one first server (OS) are browsed to determine the available content and the available encodings of the content. The rendering capabilities of the at least one renderer (UR) are determined. The rendering capabilities of the at least one renderer (UR) are compared with the available content and the available encoding of the content according to the content directory service of the at least one server (OS). The content directoryservice (CDS) of the at least one server (OS) is updated.

Abstract: A receiver apparatus (1) for receiving a signal over a fading channel comprises a frequency domain interpolation unit (16) with a filter unit (10), a power comparison unit (20), and a processing unit (21). The filter unit (10) comprises a first filter element (11), which is a reference filter, and a second filter element (12). The first filter element (11) is arranged as large-band filter. The power comparison unit (20) compares the power of the signal filtered with said second filter element (12) with the power of the signal filtered with said first filter element (11). The processing unit (21) determines an appropriate filter length for a third filter element (13) of the filter unit (10) on the basis of this comparison. Thereby, a trade-off is made between an additional power received due to a long echo and an additional Gaussian noise power.