Abstract: The invention relates to a method of manufacturing a semiconductor device (10) comprising a substrate (11) and a semiconductor body (12) in which at least one semiconductor element (1) is formed, wherein on the substrate (11) a semiconductor layer (2) is formed comprising a mixed crystal of silicon and germanium, further called the silicon-germanium layer (2) and having a lower surface close to the substrate (11) and an upper surface more remote from the substrate (11), and wherein the silicon-germanium layer (2) is subjected to an oxidizing treatment at a surface of the silicon-germanium layer (2) while the other surface of the silicon-germanium layer (2) is protected against the oxidizing treatment by a blocking layer (3).

Abstract: An apparatus and method for matched variable resistor structures to electrically measure unidirectional misalignment of stitched masks for etched interconnect layers includes a first test pad and a second test pad for measuring resistance therebetween; a first resistive element electrically connected at a first end to the first test pad; and, a second resistive element electrically connected at a first end to the second test pad. The first resistive element and the second resistive element are electrically connected by a vertical offset. The resistance measured between the first test pad and the second test pad is variable in accordance with an alignment of the first resistive element and the second resistive element relative to the vertical offset. An indicator may optionally provide an indication that the resistive elements are in alignment.

Abstract: In an example embodiment, there is a package substrate (200) for mounting an integrated circuit (IC) device (205). The package substrate comprises an IC device placement area (290) surrounded by pad landings (215). For placing surface mount devices in vicinity of the pad landings, there is a plurality of component pads (235a, 235b, 235c, 235d). The plurality of component pads surrounds the pad landings (215). A plurality of device pins (225a, 225b, 225c, 225d, 245a, 245b, 245c, 245d) surrounds the component pads. One or more of the plurality of device pins, having fine-pitch conductive paths (270), couple the one or more of the plurality of device pins to a set of corresponding pad landings (215) or to a set of corresponding component pads; the fine-pitch conductive paths (270) traverse regions between the plurality of component pads.

Abstract: Pixels of an image (200) are coded as colour vectors specified by RGB values. The image (200) is filtered by calculating new colour vectors for the pixels on a pixel by pixel basis. A new colour vector for a subject pixel (201) is calculated from the average of neighbour pixels (203) in a window (202) around the subject pixel (201). A first threshold is calculated from the standard deviation of the colour vectors of the neighbour pixels (203) in the window (202). A second threshold is calculated from the median maximum difference between the values defining the colour vectors of the respective neighbour pixels (203) in the window (202) and the standard deviation of the values. Only neighbour pixels (203) having a colour vector that differs from the colour vector of the subject pixel (201) by less than or the same as the first and second thresholds are used in calculation of the new colour vector for the subject pixel (201).

Abstract: A system and method for replacing data in a cache utilizes cache block validity information, which contains information that indicates that data in a cache block is no longer needed for processing, to maintain least recently used information of cache blocks in a cache set of the cache, identifies the least recently used cache block of the cache set using the least recently used information of the cache blocks in the cache set, and replaces data in the least recently used cache block of the cache set with data from main memory.

Abstract: A reference voltage that is consistent over various operational conditions and uses low power is provided. According to an example, an internal temperature-compensated voltage (e.g., vdd_int in 200) is generated from a power supply (e.g., vdd in 200), and a reference voltage (e.g., vref in 200) is generated from the internal voltage. The reference voltage is stored on a storage circuit (e.g., 430) that is coupled (charged) and refreshed under conditions, relative to circuit characteristics, that make low and ultra-low power operation possible.

Abstract: A biosensor device (100) for sequencing biological particles (102), the biosensor device (100) comprising at least one substrate (104), a plurality of sensor active regions (106) provided on each of the at least one substrate (104) and each comprising a primer (108) having a sequence being complementary to a part of a sequence of the biological particles (102) and enabling generation of fragments having a sequence being inverse to a part of the sequence of the biological particles (102) at the primer (108), and a determination unit (114) adapted for individually determining a size of the fragments generated at the primer (108) of each of the plurality of sensor active regions (106), the fragment replication being terminated in the presence of replication terminating sequence units (116 to 119).

Abstract: Integrated circuits (1) on a wafer comprise a wafer substrate (2) and a structure applied on a surface (4) of the wafer substrate (2). The structure forms a plurality of integrated circuits (1) formed on the wafer substrate (2) and the integrated circuits (1) are separated by saw lines (6, 7). The structure comprises a plurality of superposed layers (9a-9e) formed on the wafer substrate (2) and a top layer (10) formed on the superposed layers (9a-9e). The integrated circuit (1) on the wafer further comprise a plurality of alignment marks (3) intended for aligning a separating device (18) for separating the integrated circuits (1) on the wafer into individual integrated circuits (1) during a separation process, wherein the alignment marks (3) are formed from at least one of the superposed layers (9a-9e).

Abstract: The present invention relates to a method of and arrangement for determining non-linear behavior of a device (40) under test, wherein the device (40) is excited by a test signal on relevant device terminals under different termination conditions and the emitted signals at the fundamental and harmonic frequencies are measured at the relevant device terminals. Then, calibration measurements taken on calibration standards of known impedance and linearity are performed to derive parameters needed to correct the raw data read by the measurement for cable loss and delay and for non-linear behavior of the measurement system. Finally, non-linear scattering or admittance parameters are extracted from the error corrected measurements taken at different excitation and termination conditions. Thereby, the non-linear behavior can be more accurately characterized, modeled and understood.

Abstract: A method of producing an integrated circuit (700) using a system-on-chip (SoC) architecture includes providing a first circuit (710) in a first island of synchronicity (IoS); and providing a source-synchronous data link (755/757, 765/767) between the first circuit (710) in the first IoS and a hard core (720) in a second IoS for communicating n-bit data elements between the first circuit (710) and the hard core (720). The source-synchronous data link (755/757, 765/767) includes a set of n data lines (755, 765) for transporting the n-bit data elements between the first circuit (710) and the hard core (720), and a source-synchronous clock line (757, 767) for transporting a source clock between the first circuit (710) and the hard core (720) for clocking the n-bit data elements. The hard core (720) does not include a bus interface adaptor for interfacing with the source-synchronous data link (755/757, 765/767).

Abstract: A MEMS microphone (100) is disclosed comprising: a substrate (101), a membrane (102) attached to the substrate (101), and an electrode (104) attached to the substrate (101), wherein the membrane (102) and the electrode (104) have the same resonance frequency.

Abstract: A magnetic field sensor circuit comprises a first magneto-resistive sensor (Rx) which senses a first magnetic field component in a first direction to supply a first sense signal (Vx). A first flipping coil (FC1) applies a first flipping magnetic field with a periodically changing polarity to the first magneto-resistive sensor (Rx) to cause the first sense signal (Vx) to have alternating different levels synchronized with the first flipping magnetic field. A second magneto -resistive sensor (Ry) senses a second magnetic field component in a second direction different than the first direction to supply a second sense signal (Vy). A second flipping coil (FC2) applies a second flipping magnetic field with a periodically changing polarity to the second magneto -resistive sensor (Ry) to cause the second sense signal (Vy) to have an alternating different levels synchronized with the second flipping magnetic field. The first flipping magnetic field and the second flipping magnetic field have a phase shift.

Abstract: In a method of allocating digital data (55a, 55b) coming from transponders, a reader (1) receives a first signal (13) that comprises a first signal component (7) coming from a first transponder (2) and a second signal component (8) coming from a second transponder (3). The digital data (55a) coming from the first transponder (2) are encoded in the first signal component (7) and digital data (55b) coming from the second transponder (3) are encoded in the second signal component (8). Second and third signals (10, 11) are generated by subjecting the first signal (13) to an in-phase and to an in-quadrature demodulation. The digital data (55a, 55b) of the first and second transponders (2, 3) are encoded in the second and third signals (10, 11). Clusters (51-54) of the digital data (55 a, 55b) associated with a constellation diagram, which is related to the second and third signals (10, 11), are allocated to the first and second transponder (2, 3).

Abstract: Consistent with an example embodiment, an edge-rate control circuit arrangement (300) for an I2C bus application comprises a first circuit stage (10, M1, M3), responsive to a state transition of a received signal. A second circuit stage (310, 25, 20, 35, 45, M4, ESD) is responsive to the state transition of the received signal and includes drive circuitry (M4) that is activated in response to the state transition of the received signal in order to provide an edge-transition signal for an I2C bus, and regulation circuitry (310, R1, R2, M0, M2) adapted to control the drive circuit and regulate a transition rate for the edge-transition signal, the transition rate being greater than a transition rate of the received signal at the first circuit stage and greater than a minimum and less than a maximum transition rate designated for communication on the I2C bus.

Abstract: The invention discloses a method and a circuit for preventing clipping of an audio signal. The method comprises determining the highest amplitude frequency components of the audio signal in the frequency domain, and then reducing the amplitudes of these frequency components until a level of clipping of the audio signal falls below a predetermined level.

Abstract: An LC oscillator is provided that achieves improved phase noise performance. A variable frequency oscillator includes a variable supply source (I), an oscillator tank circuit (T), a variable capacitance circuit (VC1) comprising MOS switches, and an oscillator tank voltage common mode adjustment circuit (R). When the capacitance of the variable capacitance circuit is varied to vary an output frequency of the variable frequency oscillator, the common mode voltage is adjusted to reduce transitions of the MOS switches between an inversion state and a depletion state during excursions of an output signal through one cycle of oscillation.

Abstract: An integrated circuit (10) comprises a functional circuit (12a-c) that contain information that must be secured against unauthorized access. The integrated circuit comprises a test access circuit (14, 16) coupled to the functional circuit (12a-c), and a plurality of fuse elements (18) coupled to the test access circuit (14, 16). The fuse elements (18) are connected in a circuit configuration that makes the functional circuit (12a-c) consistently accessible via the test access circuit (14, 16) only when first fuse elements (18) of the plurality are in a blown state and second fuse elements (18) of the plurality are in a not-blown state. As a result the integrated circuit can be tested after selectively blowing all of the first fuse elements (18). After testing at least part of the second fuse elements (18) is blown.

Abstract: An inductive component for a DC/DC converter is made by transferring a copper track (2) from a copper substrate (1) to a first ferrite plate (3). A second ferrite plate (5) is attached by glue to the first ferrite plate so that the track (2) forms an inductor coil sandwiched between the two ferrite plates (3,5). One of the plates has holes (4) in registration with the terminals of the coil, and these holes are filled with solder (5) to provide externally accessible contacts.

Abstract: A method of processing pixels of an image comprises determining the most homogenous region of the image, calculating a threshold (th) according to the content of the determined region, selecting pixels in the image according to the calculated threshold (th), and applying a gain to the selected pixels. The method can also further comprise calculating the gain according to the content of the image.

Abstract: A data processing system comprises multiple data processing nodes that communicate with one another using the FlexRay protocol. Each respective node works according to a respective schedule based on a repetitive sequence of cycles, each cycle having a sequence of time slots. Each node executes instructions, one per time slot, if any. The instructions are stored in a memory. Each instruction is identified by the relevant cycle number and time slot number in the relevant cycle. Accordingly, the combination of cycle number and slot number identify a memory address. Typical instructions appear more than once in the repetitive sequence of cycles for a node. This temporal pattern of occurrences of the same instruction at a node is used to modify the generation of the memory addresses, so that the same memory address is generated each time the instruction is needed. This makes efficient use of storage space.