Patents Assigned to NXP
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Patent number: 7804165Abstract: A device (1) comprising a sensor module (2) with a package (3) is produced at reduced costs by providing the package (3) with two or more substrates (4,5) each with a functional layer (14,15), at least one sensor (24,25) such as a magnetometer and/or an accelerometer being located in at least one functional layer (14,15), and by providing the package (3) with a system comprising solder bumps (7-12) for aligning the functional layers (14,15).Type: GrantFiled: April 27, 2006Date of Patent: September 28, 2010Assignee: NXP B.V.Inventors: Hans M. B. Boeve, Teunis J. Ikkink, Nicolaas J. A. Van Veen
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Publication number: 20100237351Abstract: A planar double-gate transistor is manufactured wherein crystallisation inhibitors are implanted into the channel region (16) of a semiconductor wafer (10), said wafer having a laminate structure comprising an initial crystalline semiconductor layer (14) adjacent an amorphous semiconductor layer (12). Upon heating, partial re-growth of the amorphous semiconductor layer is restricted in the channel area thus allowing for the thickness of the source/drain extension regions to be increased whilst maintaining a thin channel. Any remaining amorphous material is selectively removed leaving a cavity to allow for the forming of gate electrodes (30,32) on opposing sides of the channel region. The invention can be exploited to a greater extent by providing an amorphous layer on both sides of the initial crystalline semiconductor layer thus providing for re-growth limitation in two directions.Type: ApplicationFiled: August 1, 2007Publication date: September 23, 2010Applicant: NXP, B.V.Inventor: Bartlomiej J. M. Pawlak
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Publication number: 20100239109Abstract: An acoustic device (500), comprising an oscillatory membrane (501) which comprises a transducing element (503) and a frame (504) adapted for accommodating the membrane (501) in an accommodation plane, wherein the membrane (501) is accommodated in the frame (504) in such a manner that a translational motion of the membrane (501) in at least one direction of the accommodation plane is made possible.Type: ApplicationFiled: May 6, 2007Publication date: September 23, 2010Applicant: NXP B.V.Inventors: Josef Lutz, Susanne Windischberger
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Publication number: 20100241812Abstract: Data from a shared memory (12) is processed with a plurality of processing units (11). Access to a data object is controlled by execution of acquire and release instructions for the data object, and wherein each processing unit (11) comprises a processor (10) and a cache circuit (14) for caching data from the shared memory (12). Instructions to access the data object in each processor (10) are executed only between completing execution of the acquire instruction for the data object, and execution of the release instruction for the data object in the processor (10). Execution of the acquire instruction is completed only upon detection that none of the processors (10) has previously executed an acquire instruction for the data object without subsequently completing execution of a release instruction for the data object.Type: ApplicationFiled: October 14, 2008Publication date: September 23, 2010Applicant: NXP B.V.Inventor: Marco Jan Gerrit Bekoou
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Publication number: 20100238720Abstract: An electronic device (100) comprising a heat transfer structure (103) and a phase change structure (104) which is convertible between two phase states by heating, wherein the phase change structure (104) is electrically conductive in at least one of the two phase states, wherein the heat transfer structure (103) is arranged to be heated by radiation (106) impinging on the heat transfer structure (103), wherein the phase change structure (104) is thermally coupled to the heat transfer structure (103) so that the phase change structure (104) is convertible between the two phase states when the radiation (106) impinges on the heat transfer structure (103).Type: ApplicationFiled: March 19, 2008Publication date: September 23, 2010Applicant: NXP B.VInventors: David Tio Castro, Karen Attenborough
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Publication number: 20100237434Abstract: The invention relates to a semiconductor device (10) with a substrate (11) and a semiconductor body (12) of silicon which comprises an active region (A) with a transistor (T) and a passive region (P) surrounding the active region (A) and which is provided with a buried conducting region (1) of a metallic material that is connected to a conductive region (2) of a metallic material sunken from the surface of the semiconductor body (12), by which the buried conductive region (1) is made electrically connectable at the surface of the semiconductor body (12). According to the invention, the buried conducting region (1) is made at the location of the active region (A) of the semiconductor body (12). In this way, a very low buried resistance can be locally created in the active region (A) in the semiconductor body (12), using a metallic material that has completely different crystallographic properties from the surrounding silicon. This is made possible by using a method according to the invention.Type: ApplicationFiled: June 22, 2006Publication date: September 23, 2010Applicant: NXP B.V.Inventors: Wibo D. Van Noort, Jan Sonsky, Philippe Meunier-Beillard, Erwin Hijzen
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Publication number: 20100237955Abstract: A voltage reference connects to a voltage-to-current converter to generate a reference current dependent on the reference voltage. Outputs of a toggle-type flip flop connect to switching transistors controlling the reference current charging capacitors. The toggling of the flip-flop is controlled by comparing the capacitor voltages to the reference voltage, such that the toggle frequency is proportional to the time charging the capacitors. Optionally, temperature compensation data, representing a magnitude and direction rotation of the frequency versus temperature characteristic is stored and, based on a sensed temperature, retrieved to modify the reference current.Type: ApplicationFiled: March 18, 2009Publication date: September 23, 2010Applicant: NXP B.V.Inventor: Kevin Mahooti
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Publication number: 20100237999Abstract: A radio frequency transponder (1) comprising a substrate (2); an integrated circuit (3) disposed on said substrate (2); and an antenna (4) disposed on said substrate (2) and coupled to the integrated circuit (3); wherein the antenna (4) comprises a first conducting arm (4.1) having a substantially U-shaped structure and a second conducting arm (4.2) having an at least partly meander-shaped structure.Type: ApplicationFiled: November 12, 2008Publication date: September 23, 2010Applicant: NXP B.V.Inventor: Achim Hilgers
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Publication number: 20100237919Abstract: Edge-rate control circuits and methods are implemented using a variety of arrangements and methods. Using one such method, an output signal of a bus is controlled by decoupling a feedback capacitor (116) from a gate of a transistor (108) using an isolation switch (106). The transistor (108) is used to control the output signal. A predetermined amount of charge is removed from the feedback capacitor (116) using a charge distribution capacitor (114) that is selectively coupled to the feedback capacitor (116) using a switch (112). The switch (112) is enabled in response to the output signal reaching an output voltage and disabled in response to the charge distribution capacitor (114) reaching a reference voltage.Type: ApplicationFiled: March 31, 2007Publication date: September 23, 2010Applicant: NXP B.V.Inventors: Joseph Rutkowski, Alma Anderson
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Patent number: 7800448Abstract: An integrated Doherty amplifier structure comprises an input bond pad (IBP), and an output bond pad (OBP). A first transistor (T1) forms the peak amplifier stage of the Doherty amplifier and has a control input (G1) to receive a first input signal (IS1) being an input signal of the Doherty amplifier, and has an output (D1) to supply an amplified first input signal (OS1) at an output of the Doherty amplifier A second transistor (T2) forms a main amplifier stage of the Doherty amplifier and has a control input (G2) to receive a second input signal (IS2) and has an output (D2) to supply an amplified second input signal (0S2). The first input signal (IS1) and the second input signal (IS2) have a 90° phase offset. A first bond wire (BW1) forms a first inductance (L1), and extends in a first direction, and is arranged between the input bond pad (IBP) and the control input (G1) of the first transistor (T1).Type: GrantFiled: April 11, 2007Date of Patent: September 21, 2010Assignee: NXP B.V.Inventor: Igor Blednov
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Patent number: 7800811Abstract: The spatial light modulator device (SLM) for providing a spatial light pattern which is alterable in response to an electric signal comprises a first modulator element (ME1) and a second modulator element (ME2). The first light beam (LB1) processed by the first modulator element (ME1) and the second light beam (LB2) processed by the second modulator element (ME2) can be superimposed for forming the spatial light pattern. In this way a defect in the first modulator element (ME1) can be compensated a corresponding pixel of the second modulator element (ME2). The spatial light pattern provided by the first modulator element (ME1) and the second modulator element (ME2) are complementary and combine to the desired spatial light pattern. The spatial light modulator device (SLM) may be used in a lithography apparatus (LA) or a display device (DD).Type: GrantFiled: May 8, 2006Date of Patent: September 21, 2010Assignee: NXP B.V.Inventor: Erik Jan Lous
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Patent number: 7801486Abstract: The invention relates to a communication system comprising:—a master handheld apparatus (100) comprising a first near field communication device a first wireless communication device, a current session being held by the master handheld apparatus (100), a slave handheld apparatus (130) comprising a second near field communication device and a second wireless communication device, the first and second near field communication devices being adapted to exchange identification information when they are held next to each other so as to initiate a communication link (140) between the first and second wireless communication devices, the first and second wireless communication devices then enabling the slave handheld apparatus (130) to join the current session through the communication link (140).Type: GrantFiled: December 14, 2005Date of Patent: September 21, 2010Assignee: NXP B.V.Inventor: Laurent Barnier
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Publication number: 20100231252Abstract: An integrated circuit (200) comprises a functional block (130) conductively coupled to a supply rail (110) via one or more switches (115). The IC further comprises selection means (220) responsive to a test enable signal for activating the one or more switches (115) in a test mode of the IC and evaluation means such as a comparator (230) having a first input coupled to a reference signal source (215) and having a second input coupled to a node (225) between the one or more switches (115) and the functional block (130) for evaluating the behaviour of the one or more switches (115) based on the reference signal and a signal from the node (225). Thus, the present invention provides a design for testability solution for testing power switches.Type: ApplicationFiled: January 5, 2007Publication date: September 16, 2010Applicant: NXP B.V.Inventors: Sandeepkumar Goel, Jose De Jesus Pineda De Gyvez, Rinze L.M.P. Meijer
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Publication number: 20100231765Abstract: Method and apparatus for demosaicing a mosaic pattern of a color picture. To improve the picture quality, especially in case of a non-uniform mosaic pattern, a kernel of the mosaic pattern is selected, and the pixel values of the kernel are multiplied by coefficients that comply with a non-linear bi-dimensional interpolation algorithm. Additionally the pixels of the selected kernel may be multiplied by sharpening coefficients that comply with a derivative of the non-linear bi-dimensional interpolation algorithm.Type: ApplicationFiled: March 23, 2007Publication date: September 16, 2010Applicant: NXP B.V.Inventor: Christophe Kefeder
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Publication number: 20100231171Abstract: The present invention relates to a multi-purpose battery charging circuit configuration able to be selectively in a simple charge mode when intended for low-end solutions (option 3) or in a charge-and-play mode when intended for medium- and high-end solutions (options 1 and 2 respectively), while maintaining the supply voltage of any portable and mobile electronic devices with an acceptable noise level. The selection will be made possible by the use of multiplexers (MUX1, MUX2). If the option 1 is chosen, the bi-directional switching device (210) will be controlled by a driver circuit (340) for allowing the current which flows through it towards the battery (20) to strongly increase and thereby maintaining the voltage across the circuitry (10) at a value slightly greater than the voltage across the battery (20).Type: ApplicationFiled: August 7, 2006Publication date: September 16, 2010Applicant: NXP B.V.Inventor: Guillaume De Cremoux
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Publication number: 20100231801Abstract: An automatic gain control (AGC) circuit based on a cascade of a step automatic gain control unit and a second automatic gain control unit connected to adjust their gain in a synchronized manner to result in a combined impulsive gain variation. Hereby it is possible, e.g. to use a step automatic gain control unit instead of a continuous automatic gain control unit in an RF part of a TV tuner without resulting in visual artifacts—this applies both for digital and analog TV tuners. According to a preferred embodiment, the synchronization between the two automatic gain control units may be achieved by the first automatic gain control unit generating a control signal upon gain adjustment, this control signal serving to speed up a loop bandwidth controlling gain change of the second automatic gain control unit. In another embodiment, the control signal generated by the first automatic gain control unit is used to control a gain step of the second automatic gain control unit.Type: ApplicationFiled: March 21, 2007Publication date: September 16, 2010Applicant: NXP B.V.Inventors: Luca Lococo, Francois Pichon, Jan Van Sinderen
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Publication number: 20100230673Abstract: The invention relates to a semiconductor fuse structure comprising a substrate (1) having a surface, the substrate (1) having a field oxide region (3) at the surface, the fuse structure further comprising a fuse body (FB), the fuse body (FB) comprising polysilicon (PLY), the fuse body (FB) lying over the field oxide region (3) and extending into a current-flow direction (CF), wherein the fuse structure is programmable by means of leading a current through the fuse body (FB), wherein the fuse body (FB) has a tensile strain in the current-flow direction (CF) and a compressive strain in a direction (Z) perpendicular to said surface of the substrate (1). The invention further relates to methods of manufacturing such a semiconductor fuse.Type: ApplicationFiled: June 6, 2007Publication date: September 16, 2010Applicant: NXP B.V.Inventors: Claire Ravit, Tobias S. Doorn
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Publication number: 20100230786Abstract: It is described a procedure for the integration of semiconductor incompatible materials in a process family created for the production of passive electric components and active electric components formed within integrated circuits. The procedure is applicable in known techniques like bipolar, MOS or BIMOS processes for semiconductor production. The modular concept of the described procedure may combine diodes, resistors and capacitors, which components are made from different materials. The provision of an encapsulation material for a semiconductor incompatible material enables the manufacturing of integrated circuits even within a sensitive environment with respect to contaminations originating from the semiconductor incompatible material. The encapsulation is provided early within the manufacturing process such that the risk for a contamination may be reduced to a minimum.Type: ApplicationFiled: January 25, 2007Publication date: September 16, 2010Applicant: NXP B.V.Inventor: Wolfgang Schnitt
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Publication number: 20100230808Abstract: The present invention relates to a semiconductor component that has a substrate and a projecting electrode. The projecting electrode has a substrate face, which faces the substrate and which comprises a first substrate-face section separated from the substrate by a gap. The gap allows a stress-compensating deformation of the projecting electrode relative to the substrate. The substrate face of the projecting electrode further comprises a second substrate-face section, which is in fixed mechanical and electrical connection with the substrate. Due to a smaller footprint of mechanical connection between the projecting electrode and the substrate, the projecting electrode can comply in three dimensions to mechanical stress exerted, without passing the same amount of stress on to the substrate, or to an external substrate in an assembly. This results in an improved lifetime of an assembly, in which the semiconductor component is connected to an external substrate by the projecting electrode.Type: ApplicationFiled: August 13, 2007Publication date: September 16, 2010Applicant: NXP, B.V.Inventor: Jasper Joerg
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Publication number: 20100234209Abstract: The present invention relates to particles comprising a core and a shell, a method of producing said particle, various uses of said particle as well as various products comprising said particle. The particle according to the invention may be used as photocatalyst, as antibacterial agent, as cleaning agent, as anti-fogging agent and as decomposing agent. Furthermore the particle is applicable as solar cells.Type: ApplicationFiled: October 13, 2008Publication date: September 16, 2010Applicant: NXP B.V.Inventors: Yukiko Furukawa, Olaf Wunnicke, Robertus A. M. Wolters, Nynke Verhaegh