Abstract: A method of masking a current requirement of an electronic circuit (100) is provided, wherein the method comprises determining a current level required by the electronic circuit (100) and a corresponding point in time said current level is required by the electronic circuit (100), choosing a current level corresponding to a current level which is equal or higher than the determined current level, and switching a current level supplied to/consumed by the electronic circuit (100) to the chosen current level at a time instant deviating from the determined point in time.

Abstract: A controllable-gain circuit (TI, Rt, TS1, . . . , TS4) provides a first and a second pair of complementary gain-controlled signals (Ip1, Ip3; Ip2, Ip4) in response to an input signal (RFI). In each pair, one gain-controlled signal (Ip1, Ip2) is the input signal amplified with a gain G comprised in a range between a minimum gain Gmin and a maximum gain Gmax. The other gain-controlled signal (Ip3, Ip4) is the input signal amplified with complementary gain Gmax-G. A fixed-gain output circuit (Rfg, Nfg) makes a weighed sum (Ip1*Rfg+Ip3*Rfg) of one and the other gain-controlled signal in the first pair of complementary gain-controlled signals. The respective weighing factors for one and the other gain-controlled signal are substantially similar (Rfg). A controllable-gain output circuit (Rlg, Rhg, Nlg, Nhg) makes a weighed sum (Ip2*Rlg+Ip4*(Rlg+Rhg)) of one and the other gaincontrolled signal in the second pair of complementary gain-controlled signals.

Abstract: A duty-cycle modulated bit signalling method and circuit, comprising: signaling bits by virtue of a duty-cycle ratio; wherein the duty-cycle ratio is varied dependent upon the transmission rate of the signalling. A bit period comprises a long phase and a short phase and the duty-cycle therebetween is varied such that the ratio between the duration of the long phase and the duration of the short phase is increased for decreasing transmission rate. The duty-cycle ratio is varied dependent upon the transmission rate of the signalling according to one or more ranges of transmission rate. In a higher transmission rate range the duty-cycle is defined as a fixed ratio, and in a lower transmission range the duty-cycle is defined by a fixed length of the short phase of the bit period.

Abstract: The present invention relates to a method for thermal stress reduction on a wafer, comprising the steps of providing a patterned wafer with saw lanes between adjacent dies, forming thin holes within the silicon substrate, which holes create a dotted groove in the saw lanes, and wherein no second layer on an opposing side of the wafer is formed, a patterned wafer obtained by said method. The forming of the holes is preferably combined with other processing steps or another step to avoid additional operations and manipulations prior to, or after standard wafer processing, and it therefore optimizes fabrication quality and costs. Preferably the holes within the silicon substrate having a depth of more than 3 to 50 ?m, preferably from 5-40 ?m, like 20 ?m.

Abstract: A star network (1) having a star coupler (14) and at least a first and second network branch (112, 122), wherein each network branch (112, 122) comprises at least one network node (110, 120) and a bus driver (11, 12) connected between the star coupler (14) and the at least one network node (110, 120). A first bus driver (11) of the first network branch (112) is adapted to detect a symbol pattern comprising at least two predetermined equal control symbols, which are transmitted from the first network node (110) to the second network node (120), wherein a control symbol is part of a control pattern. The control pattern is used to force at least the second network node (120) to switch into a predetermined state. The first bus driver (11) is disabling the first network branch (112) from the star network (1) based on whether the transmitted symbol pattern is detected. By using the protection mechanism a reliable detection of babbling idiots is provided.

Abstract: The present invention relates to a method of forming a micro cavity having a micro electrical mechanical system (MEMS) in a process, such as a CMOS process. MEMS resonators are being intensively studied in many research groups and some first products have recently been released. This type of device offers a high Q-factor, small size, high level of integration and potentially low cost. These devices are expected to replace bulky quartz crystals in high-precision oscillators and may also be used as RF filters.

Abstract: It is an object of the invention to improve the performance of a multitasking data processing system in which at least one exclusive resource is used for executing at least two task flows. The method according to the invention achieves this by using a so-called master schedule, which is used as a template to construct the schedules for individual task flows. The term master schedule refers to a set of reservations of the exclusive resources for task flows.

Abstract: A method for verifying a software application to a user of a device such as a mobile phone. The device receives (102) the software application, for example a Java ME MIDlet, and checks (104) a signature associated with the software application. Where the signature is recognised, the phone indicates (108) this status to the user, for example by displaying the familiar padlock icon. The mobile phone then establishes (110) a secure code known only to the user and a trusted entity, the entity being for example the manager of the Java ME environment. The device identifies (114) the software application to the trusted entity which then checks (116) the status of the software application. If the status is verified, the entity sends (118) the status to the device; which in turn indicates (120) the secure code to the user, for example as an additional displayed number, pictogram or the like.

Abstract: An embedded device (1) having a memory (2) that is organized to store both data objects (DO1-DOx) and meta data (MD) which describes the locations at which the data objects are stored in the memory (2), the embedded device (1) which is connectable to a remote defragmentation device (3) is disclosed. The embedded device (1) is adapted to transmit, at the request of the defragmentation device (3), the meta data (MD) and optionally the data objects (DO1-DOx) stored in the memory (2) to the defragmentation device (3) and, in accordance with instructions and data received from the defragmentation device (3), to update in its memory (2) the meta data (MD) and to store the data objects (DO1-DOx) at locations as defined in the updated meta data (MD).

Abstract: A method of forming a localized SOI structure in a substrate (10) wherein a trench (18) is formed in the substrate, and a dielectric layer (20) is formed on the base of the trench (18). The trench is filled with semiconductor material (22) by means of epitaxial growth.

Abstract: A process for forming a single crystal layer of one material type such as III-V semiconductor) onto a substrate of a different material type such as silicon. A substrate of a first material type is provided. At least one discrete region of catalyst material is deposited onto the substrate, the discrete region defining a seed area of the substrate. A second material type such as III-V semiconductor is grown as a single crystal nanowire onto the substrate between the substrate and catalyst material, the nanowire of second material type extending upward from the substrate with lateral dimensions not substantially exceeding the seed area. After growth of the nanowire, growth conditions are changed so as to epitaxially grow the second material type laterally from the single crystal nanowire in a direction parallel to the substrate surface.

Abstract: A MEMS multiaxial inertial sensor of angular and linear displacements, velocities or accelerations has four comb drive capacitive sensing elements (18) integrated on a planar substrate (12), each having an output responsive to displacement along a Z axis, and responsive to a displacement along X or Y axes. The sensing elements are located at different parts of the substrate on both sides of the X axis and the Y axis, the outputs being suitable for subsequently deriving linear displacements along any of the X, Y or Z axes and angular displacements about any of the X, Y or Z axes. Fewer sensing elements are needed to sense in multiple directions, making the device more cost effective or smaller. Linear or angular movement is determined from combinations of the sensor signals.

Abstract: A chip card (1) comprises a chip card controller (3), access to at least one power source (7, 8, 10), a display (6), and a display driver (5) operatively coupled to the chip card controller (3), to the display (6), and to the at least one power source (7, 8, 10). The display driver (5) is configured to drive the display (6) and the display driver (5) comprises, as an integral part, a power management functionality (11) configured to manage power that comes from the at least one power source (7, 8, 10) for at least the display driver (5).

Abstract: In a method of manufacturing an antenna (11) formed on a substrate (1) an antenna structure (2) is formed on the substrate (1). The antenna structure (2) comprises an area (3) which initially is electrically short-circuited and is designed to be turned into an antenna contact (4a,4b) to be contacted with contacts (12,13) of an integrated circuit (IC). The antenna contact (4a,4b) is formed by mechanically separating the electrically short-circuited 5 area (3) particularly utilizing cutting or stamping means (5).

Abstract: The present invention relates to a method and system for a digital image stabilization intended to remove unwanted camera movement or jitter, both translational and rotational jitter. The system comprises the following means: 1) a motion estimation stage (10) of the global motion of the camera: block motion vectors are calculated for specific parts of the image and global motion parameters representing the camera motion are then derived. 2) a motion/jitter filtering stage (11): the translation vector and the rotation angle are filtered separately, a boundary check being then performed for verifying if the correction thus done is not above an allowed threshold. 3) a jitter compensation stage (12): the raw sequence is compensated according to the extracted jitter and the result is a stabilized sequence.

Abstract: The invention relates to an electronic device having a semiconductor die comprising at least one RF-transistor (RFT) occupying a total RF-transistor active area (ARFT) on the die (DS). The total RF-transistor active area (ARFT) includes at least one transistor channel (C) having a channel width (W) and a channel length (L), and at least one bias cell (BC) for biasing the RF-transistor (RFT). The total bias cell active area (ABC) includes at least one transistor channel (C) having a channel width (W) and a channel length (L). The at least one bias cell (BC) occupies a total bias cell active area (ABC) on the die (SD). The total RF-transistor active area (ARFT) is substantially greater than the total bias cell active area (ABC). The total bias cell active area (ABC) has a common centre of area (COABC). The total RF-transistor active area (ARFT) has a common centre of area (COARF).

Abstract: An electrode for an ionization chamber and an ionization chamber including an electrode are provided wherein the electrode comprises a substrate comprising a first material, and a plurality of nanowires extending from the substrate and manufactured by processing the first material of the substrate.

Abstract: An electronic device comprising a passive harmonic-rejection mixer. The passive harmonic rejection mixer has an input connected to several sub-mixer stages, and the sub-mixer stages are connected to a summing module for generating the output. Each sub-mixing stage comprises a gating module and a respective amplifier, the gating module adapted to selectively pass the input signal or the input signal with inverted polarity under the control of control signals.

Abstract: Semiconductor device with a patterned pad metal layer and a patterned under-bump metallization layer being mutually electrically connected in a common contact area 22. The semiconductor device includes a first test structure 11 for determining a contact resistance between the patterned metallization layer and the patterned pad metal layer in the common contact areas 22. The first test structure includes a pad metal layer portion 24 and a metallization layer portion 18 being in electrical communication with the pad metal layer portion 24 through the common contact area 22. The first test structure 11 further includes connection areas 14, 16 that are electrically connected with each other substantially via the common contact area 22. Upon application of a current between the connection areas 14, 16 a voltage drop occurs that is representative for a voltage drop over the common contact area 22.

Abstract: Operating a wireless communications system that supports multi-user multiple-input multiple-output (MU-MIMO) communications between a base station and multiple mobile stations involves generating a channel estimation, predicting a future channel estimation from the channel estimation, precoding data in response to the predicted future channel estimation, and transmitting the precoded data.