Patents Assigned to NXP
  • METHOD AND SYSTEM FOR CONTROLLING THE ADMISSION OF A STORAGE MEANS TO A PERPHERAL BUS OF A DATA REPRODUCTION SYSTEM
    Publication number: 20100228897
    Abstract: It is an object of the invention to ensure the reliable and flawless operation of a storage means that is connected to a data reproduction system. This object will be met by a method for controlling the admission of a storage means to a peripheral bus of a data reproduction system, wherein a storage means is connected to the peripheral bus of a data reproduction system, the read latency of the storage means is determined, and it is decided based on the determined read latency whether the storage means is admitted to the peripheral bus or rejected. The latency for read requests from the storage means, for instance a USB mass storage device, will be analyzed on first insertion and the results of this analysis will be used to carry out a compatibility check of the storage means with the data reproduction system, for example a car audio system.
    Type: Application
    Filed: October 8, 2008
    Publication date: September 9, 2010
    Applicant: NXP B.V.
    Inventors: Stefan De Troch, Karl Verheyden
  • CIRCUIT ARRANGEMENT AND METHOD FOR DATA PROCESSING
    Publication number: 20100228904
    Abstract: In order to further develop a circuit arrangement (100) as well as a method of processing data to be protected against unauthorized access by means of encryption or decryption, by means of which method the data are stored in at least two memory modules (10, 12) in such way that a flexible configuration of any memory parts as main memory or redundancy memory is enabled, it is proposed to provide at least one real-time configurable redundancy concept for the memory modules (10, 12), by which the data can be stored redundantly in physically separate memory modules (10, 12).
    Type: Application
    Filed: August 6, 2007
    Publication date: September 9, 2010
    Applicant: NXP, B.V.
    Inventors: Wolfgang Buhr, Detlef Mueller
  • RF-IC PACKAGING METHOD AND CIRCUITS OBTAINED THEREBY
    Publication number: 20100224958
    Abstract: Typically, chips nowadays comprise a number of circuits as well as a number of inductors, often RF-inductors. These IC inductors are essential to realize the voltage controlled oscillators needed in the many fully integrated transceiver chips, serving a multitude of wireless communication protocols, that are provided to the market today. The present invention relates to an RF-IC packaging method, which virtually eliminates the long-range electromagnetic crosstalk between inductors and transmission lines of different parts of the circuitry.
    Type: Application
    Filed: October 23, 2008
    Publication date: September 9, 2010
    Applicant: NXP B.V.
    Inventor: Lukas Frederik Tiemeijer
  • CHARGE PUMP DC-DC CONVERTER COMPRISING SOLID STATE BATTERIES
    Publication number: 20100225278
    Abstract: An electronic device is provided which comprises a DC-DC converter. The DC-DC converter comprises at least one solid-state rechargeable battery (B1, B2) for storing energy for the DC-DC conversion and an output capacitor (C2).
    Type: Application
    Filed: June 1, 2007
    Publication date: September 9, 2010
    Applicant: NXP B.V.
    Inventors: Derk Reefman, Freddy Roozeboom, Petrus H. L. Notten, Johan H. Klootwijk
  • SYSTEM AND METHOD FOR FRAME RATE CONVERSION THAT UTILIZES MOTION ESTIMATION AND MOTION COMPENSATED TEMPORAL INTERPOLATION EMPLOYING EMBEDDED VIDEO COMPRESSION
    Publication number: 20100226435
    Abstract: A technique for frame rate conversion that utilizes motion estimation and motion compensated temporal interpolation includes obtaining a first image and a second image, where the first and second images correspond to different instances in time, compressing the second image using multiple motion vectors that result from motion estimation between the first image and the second image to generate a compressed image, and generating an interpolated image using the compressed image.
    Type: Application
    Filed: March 4, 2009
    Publication date: September 9, 2010
    Applicant: NXP B.V.
    Inventors: Abraham Karel Riemens, Onno Eerenberg, Thijs Thomas Withaar, Timo Van Roermund
  • Semiconductor Chip, Transponder and Method of Manufacturing a Transponder
    Publication number: 20100224959
    Abstract: A semiconductor chip (1, 91) for a transponder (3, 93) comprises a chip substrate (4) with a surface (5), chip terminals (6, 7) arranged on the surface (5), and a passivation layer (22) covering the surface (5) and completely covering the chip terminals (6, 7), so that an antenna (2, 30) with antenna terminals (24, 25) can be attached to the chip (1, 91) above the chip terminals (6, 7), so that the chip terminals (6, 7), the passivation layer (22) and the antenna terminal (24, 25) form first capacitors.
    Type: Application
    Filed: May 16, 2007
    Publication date: September 9, 2010
    Applicant: NXP B.V.
    Inventors: Christian Scherabon, Anton Salfener, Wolfgang Steinbauer, Joachim Heinz Schober
  • DISPLAY DEVICE AND METHOD OF PROVIDING ILLUMINATION THERETO
    Publication number: 20100225670
    Abstract: The present invention proposes a method of providing illumination for a display device including a lighting unit having a plurality of light sources (104). Desired light outputs are determined (210) for each of the light sources (104) in accordance with image data to be displayed. The desired light outputs are compared (220) to a reference light output, and the difference is used to determine a power saving factor. The desired light output for one or more light sources is then increased (230) using the power saving factor. When the lighting unit is activated in accordance with these gained light outputs, a high contrast image is rendered on the display screen, which appears particularly visually appealing to a viewer. Optional steps (312)-(316) compensate for optical cross talk between adjacent backlight segments.
    Type: Application
    Filed: June 1, 2007
    Publication date: September 9, 2010
    Applicant: NXP B.V.
    Inventors: Hendrikus C W. Groot Hulze, Theo G. Zijlman, Jeroen Den Breejen
  • APPARATUS AND METHOD FOR MAINTAINING A NEAR-ATMOSPHERIC PRESSURE INSIDE A PROCESS CHAMBER
    Publication number: 20100227480
    Abstract: A process chamber (1) is provided for a thermal treatment of a semiconductor wafer. The process chamber (1) comprises a gas injection line (4), for injecting a process gas into the process chamber (1), and a gas exhaustion line (14). A pump (8) is coupled to the gas exhaustion line (14) and maintains a pressure inside the process chamber (1) at a level that is higher than the ambient atmospheric pressure outside the process chamber (1).
    Type: Application
    Filed: June 23, 2006
    Publication date: September 9, 2010
    Applicant: NXP B.V.
    Inventor: Antonius Marinus Coenraad Petrus Van De Kerkhof
  • DATA CARRIER COMPRISING STRAIN GAUGE MEANS
    Publication number: 20100225483
    Abstract: A data carrier (2) comprises a data circuit (4) arranged on a substrate (3) and data transmission means (10) being connected to the data circuit (4). The data carrier (2) further comprises at least one strain gauge means (7) being adapted to measure strains exerted on the substrate (3) and to transmit a deactivating signal (DE) to the data circuit (4) if the measured strains exceed a defined deactivating strain threshold. If the data circuit (4) receives the deactivating signal (DE), the data circuit (4) interrupts a data exchange with an external data reader/writer (1) via the data transmission means (10).
    Type: Application
    Filed: March 23, 2007
    Publication date: September 9, 2010
    Applicant: NXP B.V.
    Inventors: Heimo Scheucher, Ewald Bergler
  • APPARATUS FOR ALIGNING AN OPTICAL DEVICE AN OBJECT, AN OPTICAL INSTRUMENT AND A SEMICONDUCTOR PROCESS SYSTEM
    Publication number: 20100223767
    Abstract: The present invention relates to an apparatus (10) for aligning an optical device with an object. The apparatus comprises, a frame (12), a support unit (16) for supporting said optical device or said object and a transportation device (14) arranged to at least tilt the support unit in relation to the frame, wherein a segment of a sphere (18, 22) is provided, which segment defines a spherical surface (20), and the tilting movement of the support unit is controlled by said spherical surface. The apparatus according to the invention allows for a tilting movement between said optical device and said object, while such movement does not lead to a shift in focus. Furthermore the invention relates to an optical instrument and a semiconductor process system comprising said apparatus.
    Type: Application
    Filed: February 1, 2007
    Publication date: September 9, 2010
    Applicant: NXP B.V.
    Inventors: Job Vianen, Jozef P.W. Stokkermans
  • LIGHT SENSOR ARRANGEMENT
    Publication number: 20100225628
    Abstract: Ambient light is sensed for use in determining luminous flux. According to an example embodiment, ambient light is sensed using two light sensor arrangements that respectively respond differently to light of different relative wavelengths. The output of the sensors is nonlinearly combined to generate data indicative of the luminous flux. This luminous flux data is used to generate a control output for controlling an electronic display.
    Type: Application
    Filed: July 30, 2008
    Publication date: September 9, 2010
    Applicant: NXP B.V.
    Inventors: Vitali Souchkov, Rob Van Dalen
  • Double gate non-volatile memory device and method of manufacturing
    Patent number: 7791128
    Abstract: The present invention relates to a non-volatile memory device on a substrate layer comprising semiconductor source and drain regions, a semiconductor channel region, a charge storage stack and a control gate; the channel region being fin-shaped having two sidewall portions and a top portion, and extending between the source region and the drain region; the charge storage stack being positioned between the source and drain regions and extending over the fin-shaped channel, substantially perpendicularly to the length direction of the fin-shaped channel; the control gate being in contact with the charge storage stack, wherein—an access gate is provided adjacent to one sidewall portion and separated therefrom by an intermediate gate oxide layer, and—the charge storage stack contacts the fin-shaped channel on the other sidewall portion and is separated from the channel by the intermediate gate oxide layer.
    Type: Grant
    Filed: September 26, 2006
    Date of Patent: September 7, 2010
    Assignee: NXP B.V.
    Inventors: Gerben Doornbos, Pierre Goarin
  • Double-gate semiconductor devices having gates with different work functions and methods of manufacture thereof
    Patent number: 7791140
    Abstract: A double-gate FinFET and methods for its manufacture are provided. The FinFET includes first and second gates (72, 74) adjacent respective sides of the fin (20), with at least a portion of the first gate facing the fin being formed of polycrystalline silicon, and at least a portion of the second gate facing the fin being formed of a metal silicide compound. The different compositions of the two gates provide different respective work functions to reduce short channel effects.
    Type: Grant
    Filed: February 2, 2007
    Date of Patent: September 7, 2010
    Assignee: NXP B.V.
    Inventors: Mark Van Dal, Radu Surdeanu
  • Trench isolation structure, semiconductor assembly comprising such a trench isolation, and method for forming such a trench isolation
    Patent number: 7791162
    Abstract: The present invention provides a trench isolation structure, comprising a trench groove (4) in a semiconductor slab (1) with a buried layer (2). The trench groove (4) is lined with first insulating material (5), then filled with a first filler material (6) up to the level of the buried layer. Then second insulating material (7), for example an oxide, is preferably applied in the volume which is surrounded by the buried layer (2). The remaining part of the trench groove (4) is either filled with second filler material (8) or with second insulating material. Said structure provides lower capacitive coupling between buried layer (2) edge and substrate (1), with improved thermal behavior. The invention furthermore provides a semiconductor assembly comprising said trench isolation structure and at least one semiconductor device, as well as a method for forming such a trench isolation structure.
    Type: Grant
    Filed: December 16, 2003
    Date of Patent: September 7, 2010
    Assignee: NXP B.V.
    Inventor: Johan Hendrik Klootwijk
  • Magnetic memory system using MRAM-sensor
    Patent number: 7791937
    Abstract: The invention relates to a Magnetic memory system (1, 20) which comprises an information layer (13) and a sensor (2, 22) for cooperating with the information layer (13). The information layer (13) comprises a pattern of magnetic bits (4a, 4b, 4c, 4d, 24a, 24c, 24d) which constitutes an array of bit locations. A bit magnetic field (3a, 3b, 3c, 3d) at a bit location represents a logical value (LO, L1/2, L1). The sensor (2, 22) comprises a magnetoresistive element (6, 26) comprising a fixed magnetic layer (7) and a free magnetic layer (8). The free magnetic layer (8) has a magnetization axis (10) along which the free magnetic layer retains a free magnetization direction (1 Ib, 1 Ic, 21b, 21c).
    Type: Grant
    Filed: January 19, 2006
    Date of Patent: September 7, 2010
    Assignee: NXP B.V.
    Inventors: Friso J. Jedema, Hans M. B. Boeve, Jaap Ruigrok
  • Method of providing enhanced breakdown by diluted doping profiles in high-voltage transistors
    Patent number: 7790589
    Abstract: A method of fabricating high-voltage semiconductor devices, the semiconductor devices and a mask for implanting dopants in a semiconductor are described.
    Type: Grant
    Filed: April 30, 2007
    Date of Patent: September 7, 2010
    Assignee: NXP B.V.
    Inventors: Paulus J. T. Eggenkamp, Priscilla W. M. Boos, Maarten Jacobus Swanenberg, Rob Van Dalen, Anco Heringa, Adrianus Willem Ludikhuize
  • On silicon interconnect capacitance extraction
    Patent number: 7791357
    Abstract: The present invention relates to a on-chip circuit for on silicon interconnect capacitance (Cx) extraction that is self compensated for process variations in the integrated transistors. The circuit (10) comprises signal generation means (20) for generating a periodical pulse signal connected to first and to second signal delaying means (31, 32) for respective delaying said pulse signal, wherein said second signal delaying means (32) are configured to have a delay affected by said interconnect capacitance (Cx); a logical XOR gate (35) for connecting respective first and said second delay signals of said respective first and second delay means (31, 32), said logical XOR gate (35) being connected to signal integrating means (40); and said signal integrating means (40) being connected to analog to digital converting means (50).
    Type: Grant
    Filed: December 19, 2005
    Date of Patent: September 7, 2010
    Assignee: NXP B.V.
    Inventors: Praveen Pavithran, Marcel Pelgrom, Jean Wieling, Hendricus Joseph Veendrick
  • Method of forming an interconnect structure
    Patent number: 7790606
    Abstract: A method of forming an interconnect structure in a semiconductor device in which via holes (62) defined in a dielectric layer are filled with a filler material (64), such as a porogen material, before a further dielectric layer (66) is deposited thereover. Trenches (72) are formed in the further dielectric layer and then the filler material exposed thereby in the via holes is removed. The method provides a robust process which affords improved via and trench profile control.
    Type: Grant
    Filed: October 5, 2007
    Date of Patent: September 7, 2010
    Assignee: NXP B.V.
    Inventor: Roel Daamen
  • Nanowire tunneling transistor
    Patent number: 7791108
    Abstract: A transistor comprises a nanowire (22, 22?) having a source (24) and a drain (29) separated by an intrinsic or lowly doped region (26, 28). A potential barrier is formed at the interface of the intrinsic or lowly doped region (26, 28) and one of the source (24) and the drain (29). A gate electrode (32) is provided in the vicinity of the potential barrier such that the height of the potential barrier can be modulated by applying an appropriate voltage to the gate electrode (32).
    Type: Grant
    Filed: January 24, 2007
    Date of Patent: September 7, 2010
    Assignee: NXP B.V.
    Inventors: Fred Hurkx, Prabhat Agarwal
  • Active shielding for a circuit comprising magnetically sensitive materials
    Patent number: 7791920
    Abstract: The present invention provides a method for providing magnetic shielding for a circuit comprising magnetically sensitive materials, comprising actively shielding the circuit from a disturbing magnetic field. A corresponding semiconductor device is also provided. The method and device allows shielding for strong disturbing magnetic fields.
    Type: Grant
    Filed: November 25, 2008
    Date of Patent: September 7, 2010
    Assignee: NXP B.V.
    Inventor: Kars-Michiel Hubert Lenssen