Abstract: Adaptive enabling and disabling is described for valley switching in a power factor correction boost converter. In one example, a boost converter control system includes an amplitude detector to receive an amplitude signal from a boost converter that is related to ringing of the boost converter output. The amplitude detector determines the ringing amplitude. A valley switching controller compares the ringing amplitude to a first high amplitude threshold when valley switching is enabled and generates a valley switching disable signal if the ringing amplitude is below the first high amplitude threshold. A cycle controller coupled to the boost converter generates a drive signal to control switching of the boost converter and coupled to the valley switching controller receives the valley switching disable signal to generate the drive signal without valley switching in response to the valley switching disable signal.

Abstract: A Radio Frequency Identification (RFID) tag is disclosed. The RFID tag includes an antenna port to receive an input AC signal and a hybrid limiter including a clamping device configured to limit a voltage of the input AC signal to a preconfigured limit. The hybrid limiter is configured to provide a stable ground reference for the clamping device.

Abstract: A one-time programmable (OTP) memory has a plurality of pages. A predefined section of each page is configured to store error policy bits. When an indicator in a first predefined location has a first value, the page is configured to store data with error correction code (ECC) bits, and when the indicator has a second value, at least a portion of the page is configured to store data with redundancy. Address translation circuitry is configured to, in response to receiving an access address, use a second predefined location of an accessed page of the plurality of pages accessed by the access address to determine a physical address in the accessed page which corresponds to the access address.

Abstract: A low voltage differential driver includes a first driver, a second driver, and an output driver. The output driver is configured to provide an output between a first output node and a second output node, and includes a current source, a first branch, and a second branch. The current source is configured to provide a source current. The current source is connected with a parallel arrangement of the first branch and the second branch. The first switch and the second switch are respectively controlled by a first switch circuit and a second switch circuit which together comprise the first driver. The third switch and the fourth switch are respectively controlled by a third switch circuit and a fourth switch circuit which together comprise the second driver. Each of the first to fourth switch circuits is connected between the upper node and the lower node.

Abstract: A battery management system comprises a first battery cell controller; a second battery cell controller, the first battery cell controller and the second battery cell controller each monitoring a plurality of battery cells; and a galvanically isolated transmission line providing a point-to-point signal transmission path between the first battery cell controller and the second battery cell controller.

Abstract: A lockstep testing system includes a lockstep controller that generates various control signals. The lockstep testing system further includes various lockstep circuitries, with each lockstep circuitry including primary and redundant functional circuits that are operable in a lockstep mode, and a fault injection circuit that receives a control signal from the lockstep controller and injects a transient fault in the corresponding lockstep circuitry. The transient fault can be injected at one of input and output stages of the primary and redundant functional circuits. Each lockstep circuitry further includes a checker circuit that tests whether the corresponding lockstep circuitry is faulty (i.e., whether the injected fault is accurately detected), and generates and provides, to the lockstep controller, a fault indication signal indicating whether the corresponding lockstep circuitry is faulty.

Abstract: A system-on-chip includes a memory, an error injection controller, an injection logic circuit, and an error detection circuit. The error injection controller is configured to generate and transmit error data, and at least one of read and write access requests associated with the memory to the injection logic circuit. The injection logic circuit is configured to access the memory based on at least one of the read and write access requests to execute at least one of read and write operations. The injection logic circuit is further configured to inject an error in at least one of first data and second data to generate at least one of erroneous first data and erroneous second data, respectively. The error detection circuit is configured to detect an error in at least one of the erroneous first data and the erroneous second data to generate an error signal.

Abstract: A radar system is disclosed that provides joint object detection and communication capabilities. The radar system includes a communication signal generator that provides a communication signal, a pre-distortion module that applies a pre-distortion to the communication signal to provide a pre-distorted communication signal, a linear frequency modulation (LFM) signal generator that provides a LFM signal, and a mixer that mixes the pre-distorted communication signal onto the LFM signal to provide a radar signal to be transmitted by the radar system. The radar system further includes an all-pass filter that filters a plurality of de-ramped reflected images of the radar signal to provide a filtered signal. Each de-ramped reflected image includes an associated image of the pre-distorted communication signal. The all-pass filter provides a linear group delay, and a non-linear phase response. The pre-distortion is an inverse of the non-linear phase response of the all-pass filter.

Abstract: Embodiments address the problem of detecting anomalies in data sets with respect to well-defined normal behavior. Deviations of data collected in real-time are detected using a previously observed distribution of data known to be benign. Embodiments provide techniques to detect varying types of anomalies by creating multiple aggregation layers having varying granularities on top of the lowest level of data collection. This allows detection of fine anomalies that strongly impact single data points, as well as coarse anomalies that detect multiple data points less strongly. Machine learning models are trained and used to compare real-time data sets against behavior of a benign data set in order to detect differences and to flag anomalous behavior.

Abstract: A method for first path acceptance for secure ranging includes determining a Channel Impulse Response (CIR) of a communication channel for a plurality of channel taps. Each channel tap corresponds to a respective one of a plurality of time slots of the CIR, wherein the CIR includes a plurality of estimated CIR values. A statistical characteristic is extracted from the estimated CIR values within a temporal range of the channel taps. The statistical characteristic is compared to a reference value to detect a distance decreasing attack.

Abstract: A type I phase locked loop (PLL) includes an oscillator and a feedback path to a phase detector. The PLL is configured to lock a first frequency and first relative phase of a first output signal to a frequency and a phase of a first input signal, and lock a second frequency and second relative phase of a second output signal to a frequency and a phase of a second input signal. A steady state phase lag of the PLL resulting from the difference between the first frequency and the second frequency is estimated, and the estimated steady state phase lag is used to determine a total phase shift (??LO,steady) between the second input signal and the second output signal. The PLL for the phase shift can be compensated. The determined total phase shift can be used in a distance estimation.

Abstract: A switched capacitor (SC) power stage includes a first stage circuit with a set of switches coupled in series, a first flying capacitor coupled to a first node between a first and second switch and to a second node between a fifth and sixth switch, a second flying capacitor coupled to a third node between the second and a third switch and to a fourth node between a seventh and eighth switch, and a third flying capacitor coupled to a fifth node between a third and fourth switch and a second terminal coupled to the second node. A control circuit establishes a first configuration of the switches to precharge the first, second, and third flying capacitors to a first voltage, and a second configuration of the switches to precharge the first and second flying capacitors to a second voltage while the third flying capacitor remains charged at the first voltage.

Abstract: An integrated circuit (IC) includes an input/output (I/O) circuitry with a first circuitry section including I/O pins and a second circuitry section including I/O pins. The first and second circuitry sections are mutually exclusive sections of the I/O ring. The first circuitry section includes a first I/O pin configured to receive an input voltage from a first energy source and a second I/O pin connectable to an external startup capacitor. A startup circuit is coupled to the first I/O pin and the second I/O pin. Upon receiving the input voltage from the first energy source, the startup circuit enters a during the startup phase and isolates the first circuitry section from the second circuitry section, and provides charge to the external startup capacitor. In response to achieving a predetermined minimum charge on the external startup capacitor, the first circuitry section is connected to the second circuitry section, and the startup phase ends and the IC transitions to a functional mode of operation.

Abstract: Methods and systems are disclosed for anti-replay protection for network packet communications. A scorecard is stored that includes packet sequence numbers for received packets associated with a network packet flow. For each received packet, an anti-replay unit accesses the scorecard for an initial check to determine if the current packet represents a late packet and/or a replay packet. After further processing, the anti-replay unit accesses the scorecard for a final check to determine if the current packet represents a replay packet. For one embodiment, the initial check uses a first window of packet sequence numbers, and the final check uses a second window of packet sequence numbers that is larger than the first window. For further embodiments, multiple processing units operate in parallel to process received packets and to share the anti-replay unit, and each processing unit requests initial and final checks for received packets it processes.

Abstract: A wireless communication system, apparatus, and methodology are described for enabling wireless communication station (STA) devices to generate a Physical Layer Protocol Data Unit (PPDU) that includes a resource unit (RU) having a size that is less than a spreading frequency block by using one or more predetermined pilot and/or data tone mapping plans to control how each pilot/data tone from the RU is distributed onto a disjoint set of pilot/data subcarriers forming a distributed RU included in the spreading frequency block, thereby accommodating transmission of wider bandwidth and multiple resource unit assignments in accordance with power spectrum density (PSD) limits provided for orthogonal frequency-division multiplexing (OFDM) modulated symbols supported by emerging 802.11 standards.

Abstract: Embodiments of a method and device are disclosed. In an embodiment, a method for synchronizing a slave clock in a Time Sensitive Network (TSN) that includes multiple Precision Time Protocol (PTP) clock domains is disclosed. The method involves determining parameters related to multiple PTP clock domains, assigning domain-specific weights to the multiple PTP clock domains based on the determined parameters, generating a control signal for a clock parameter using the domain-specific weights assigned to the multiple PTP clock domains, and adjusting the clock parameter of a slave clock in response to the control signal.

Abstract: A first device transmits to a second device a first data unit which indicates a maximum number of long training field (LTF) symbols that the first device transmits and receives for a multiple input multiple output communication. The first device receives, from the second device, a second data unit which comprises a plurality of LTF symbols up to the maximum number of LTF symbols the first device receives indicated by the first data unit. A channel estimation is performed based on the plurality of LTF symbols of the second data unit up to the maximum number of LTF symbols indicated by the first data unit to recover information in one or more fields of the second data unit. For the case when the second data unit is a trigger frame, the first device generates the third data unit with a plurality of LTF symbols up to the maximum number of LTF symbols the first device transmits indicated by the first data unit and transmits the third data unit.

Abstract: A system and method for controlling deadlock in a processing system includes asserting a deadlock condition indicator when a timer in a timer circuit has passed a predetermined period of time while a first bus master device occupies a port of a bus slave device, and an empty indicator indicates a second bus master is waiting to occupy the port of the bus slave device while the first bus master is occupying the port of the bus slave device. When the deadlock condition indicator is asserted, action can be taken by the processing system to eliminate the deadlock.

Abstract: Methods and systems for providing beamforming feedback in a communication channel are disclosed. A data packet is received at a beamformee circuitry of the first communication device configured to generate beam steering data for use by a transmitter of a second communication device. Each of a plurality of tones of the received data packet is processed to generate a compressed steering matrix corresponding to the communication channel. In parallel to the processing of the received plurality of tones, an immediate feedback packet comprising a plurality of data symbols is constructed, where the data symbols include the generated compressed steering matrix. At least a first data symbol of the immediate feedback packet is transmitted prior to completing the processing of all the plurality of tones of the received data packet.

Abstract: An RF transceiver front end includes a receiver limb including a length of transmission line, an impedance matching network, a downstream shunt switch and a downstream further receiver component and a transmitter limb. The impedance matching network is configured to transform the input impedance of the further receiver component to match the input impedance of the receiver limb when the shunt switch is open and the RF transceiver front end is operable in receiver mode. The impedance matching network is further configured to transform the input impedance of the shunt switch to present an open circuit as the input impedance of the receiver limb when the shunt switch is closed and the RF transceiver front end is operable in transmitter mode. The length of transmission line can be from zero to less than ?/4 at the operating frequency of the RF transceiver.