Patents Assigned to NXP
  • Patent number: 11565637
    Abstract: A signal processing IC unit performs image processing with respect to an output from a camera. A recognition processing IC unit performs recognition processing based on the output from the signal processing IC unit. A control IC unit outputs a control signal based on the output from the recognition processing IC unit. A first terminal is electrically connected to the recognition processing IC unit. A second terminal is electrically connected to the control IC unit. The signal processing IC unit, the recognition processing IC unit, and the control IC unit are disposed on a board. The first terminal and the second terminal are provided on an edge portion of the board.
    Type: Grant
    Filed: January 28, 2021
    Date of Patent: January 31, 2023
    Assignees: MAZDA MOTOR CORPORATION, NXP B.V.
    Inventors: Tomotsugu Futa, Kiyoyuki Tsuchiyama, Masato Ishibashi, Daisuke Hamano, Daisuke Horigome, Eiichi Hojin, Atsushi Tasaki, Yosuke Hashimoto, Yusuke Kihara, Arnaud Van Den Bossche, Ray Marshal, Leonardo Surico
  • Patent number: 11567676
    Abstract: Various embodiments relate to a memory controller, including: a memory interface connected to a memory; an address and control logic connected to the memory interface and a command interface, wherein the address and control logic is configured to receive a memory read request; a read inline encryption engine (IEE) connected to the memory interface, wherein the read IEE is configured to decrypt encrypted data read from the memory; a key selector configured to determine a read memory region associated with the memory read request based upon a read address where the data to be read is stored, wherein the read address is received from the address and control logic; and a key logic configured to select a first key associated with the determined read memory region and provide the selected key to the read IEE.
    Type: Grant
    Filed: April 30, 2021
    Date of Patent: January 31, 2023
    Assignee: NXP B.V.
    Inventors: Thomas E. Tkacik, Geoffrey Paul Waters, Mohit Mongia, James Andrew Welker, Srdjan Coric
  • Publication number: 20230023302
    Abstract: A mechanism is provided to reduce interference between vehicular radar systems through communicating radar parameters and physical orientation between vehicles and then using directional information to form clusters of radars, which will have consistent modulation parameters. Radar modulation parameters, such as starting frequency, center frequency, bandwidth, slope, ramp direction, timing, and the like for frequency-modulated continuous-wave (FMCW) radars, are adjusted to reduce or eliminate inter-cluster direct interference between clusters oriented in different directions. For other types of radars, in some embodiments, other operational parameters can be adjusted. In some embodiments, some modulation parameters also can be adjusted to reduce or eliminate intra-cluster indirect interference.
    Type: Application
    Filed: May 20, 2022
    Publication date: January 26, 2023
    Applicant: NXP B.V.
    Inventors: Sylvain Roudiere, Vincent Pierre Martinez, Didier Salle
  • Patent number: 11564275
    Abstract: Embodiments of a method and an apparatus for multi-link communications are disclosed. In an embodiment, a method for multi-link communications involves associating, by an access point (AP) multi-link device (MLD), with a non-AP MLD operating on a first set of links, and allocating, by the AP MLD, an Association ID (AID) to the non-AP MLD, such that the AID is included in a first plurality of AIDs, wherein the first plurality of AIDs does not include a first set of AIDs, and wherein at least one of the first set of AIDs are assigned to at least one of APs and Basic Service Set Identifiers (BSSIDs) on a second set of links.
    Type: Grant
    Filed: March 19, 2021
    Date of Patent: January 24, 2023
    Assignee: NXP USA, Inc.
    Inventors: Young Hoon Kwon, Liwen Chu, Hongyuan Zhang
  • Patent number: 11561255
    Abstract: An integrated circuit includes an input/output (I/O) circuit configured to receive a first signal and a second signal and a fault detection circuit. The I/O circuit includes an I/O terminal, an I/O buffer, and a pull resistor having a first terminal coupled to the I/O terminal. The fault detection circuit is configured to determine whether a predetermined number of toggles of the first signal occurs while the second signal is held at a constant logic state, assert a fault indicator when the predetermined number of toggles occurs, and negate the fault indicator when the predetermined number of toggles does not occur.
    Type: Grant
    Filed: April 15, 2021
    Date of Patent: January 24, 2023
    Assignee: NXP USA, Inc.
    Inventors: Kumar Abhishek, Xiankun Jin, Srikanth Jagannathan
  • Publication number: 20230015111
    Abstract: Aspects of the subject disclosure may include, for example, obtaining, by a first circuit of a charge pump circuit, charge sourced from a power supply operative at a first voltage level, wherein the first circuit comprises a first plurality of transistors, and wherein each of the first plurality of transistors is rated for operation at an applied voltage that is less than the first voltage level, storing the charge in a first capacitor of the first circuit at a first point in time, and transferring the charge stored in the first capacitor to a second capacitor of a second circuit of the charge pump circuit at a second point in time such that the second capacitor stores the charge, wherein the second point in time is subsequent to the first point in time. Other embodiments are disclosed.
    Type: Application
    Filed: July 15, 2021
    Publication date: January 19, 2023
    Applicant: NXP USA, Inc.
    Inventors: Mohammad Nizam Kabir, Madan Mohan Reddy Vemula, Xu Jason Ma
  • Patent number: 11557565
    Abstract: A method of forming a semiconductor device includes attaching a semiconductor die to a flag of a leadframe and forming a conductive connector over a portion of the semiconductor die and a portion of the flag. A conductive connection between a first bond pad of the semiconductor die and the flag is formed by way of the conductive connector. A second bond pad of the semiconductor die is connected to a conductive lead of the plurality by way of a bond wire.
    Type: Grant
    Filed: October 6, 2020
    Date of Patent: January 17, 2023
    Assignee: NXP USA, INC.
    Inventor: Jinbang Tang
  • Patent number: 11556394
    Abstract: An access control system controls access to a shared resource for various functional circuits. The access control system can include a comparison circuit, a processing circuit, and a selection circuit. The comparison circuit receives identification data associated with a functional circuit based on a transaction initiated by the functional circuit, and compares the identification data and reference data to generate a select signal. The processing circuit receives error data and response data outputted by the shared resource based on an execution of the transaction, and generates another response data. The selection circuit selects and outputs, based on the select signal, one of the response data outputted by the shared resource and the response data generated by the processing circuit as a transaction response that is to be provided to the functional circuit.
    Type: Grant
    Filed: May 14, 2021
    Date of Patent: January 17, 2023
    Assignee: NXP B.V.
    Inventors: Akshay Kumar Pathak, Deepak Mahajan, Arpit Gupta, Dinesh Joshi, Vivek Singh
  • Patent number: 11558047
    Abstract: Embodiments of an SMPS controller and a method for operating a switched-mode power supply (SMPS) controller are described. In an embodiment, an SMPS controller includes a gate driver circuit configured to generate a drive signal for a switch of an SMPS and a current sense electrical terminal configured to receive sensed current corresponding to the switch and to conduct driver discharge current from the gate driver circuit.
    Type: Grant
    Filed: April 6, 2020
    Date of Patent: January 17, 2023
    Assignee: NXP B.V.
    Inventor: Joan Wichard Strijker
  • Patent number: 11558074
    Abstract: Aspects of the present disclosure may involve use of a radio frequency receiver and in such a receiver, tracking multipath gains and delays of multipath reflections corresponding to an OFDM multipath transmission channel. The gains and delays are based on time-domain evolution of the channel impulse response. Multipath reflections are searched for and then used to calculate channel correlation information to provide channel estimations to aid in mitigating or cancelling distortion of the received signal.
    Type: Grant
    Filed: May 19, 2020
    Date of Patent: January 17, 2023
    Assignee: NXP B.V.
    Inventors: Özgün Paker, Arie Geert Cornelis Koppelaar
  • Patent number: 11558847
    Abstract: A first communication device prompts a plurality of second communication devices to transmit, during a contiguous time period reserved for a range measurement exchange, respective first null data packets (NDPs) at respective times. The first communication device receives first NDPs from at least some of the second communication devices during the contiguous time period, and transmits one or more second NDPs to the plurality of second communication devices. The first communication device uses reception of the first NDPs and transmission of the one or more second NDPs to determine respective ranges between the first communication device and respective second communication devices.
    Type: Grant
    Filed: November 20, 2020
    Date of Patent: January 17, 2023
    Assignee: NXP USA, INC.
    Inventors: Liwen Chu, Hongyuan Zhang, Christian R. Berger, Niranjan Grandhe, Sudhir Srinivasa, Hui-ling Lou
  • Patent number: 11557910
    Abstract: A method for power management for applications having duty-cycled high peak supply currents includes charging a buffer capacitor with a first current supplied by a battery, wherein the first current is limited by a current limiter. A load is supplied with a second current supplied by the buffer capacitor, wherein the second current comprises a pulsed current. The current limiter is controlled with at least one of a plurality of sensor inputs to limit a capacity degradation of the battery.
    Type: Grant
    Filed: December 22, 2020
    Date of Patent: January 17, 2023
    Assignee: NXP B.V.
    Inventors: Jan van Sinderen, Salvatore Drago, Gerard Villar Pique, Esa Petri Tarvainen, Wolfgang Hoess
  • Patent number: 11557544
    Abstract: A semiconductor device is provided. The device includes a semiconductor die and a launcher structure attached to a package substrate. The launcher structure includes a launcher substrate, a launcher portion formed from a conductive layer at a major surface of the launcher substrate, and a translation pad formed from the conductive layer at the major surface. The translation pad is separate from the launcher portion. A translation feature is formed on the translation pad. The translation feature is configured for alignment of a waveguide structure.
    Type: Grant
    Filed: August 27, 2020
    Date of Patent: January 17, 2023
    Assignee: NXP USA, INC.
    Inventors: Michael B. Vincent, Giorgio Carluccio, Scott M. Hayes
  • Patent number: 11557365
    Abstract: Embodiments combine error correction code (ECC) and transparent memory built-in self-test (TMBIST) for memory fault detection and correction. An ECC encoder receives input data and provides ECC data for data words stored in memory. Input XOR circuits receive the input data and output XOR'ed data as payload data for the data words. Output XOR circuits receive the payload data and output XOR'ed data. An ECC decoder receives the ECC data and the XOR'ed output data and generates error messages. Either test data from a controller running a TMBIST process or application data from a processor executing an application is selected as the input data. Either test address/control signals from the controller or application address/control signals from the processor are selected for memory access. During active operation of the application, memory access is provided to the processor and the controller, and the memory is tested during the active operation.
    Type: Grant
    Filed: August 16, 2019
    Date of Patent: January 17, 2023
    Assignee: NXP B.V.
    Inventor: Jan-Peter Schat
  • Patent number: 11558836
    Abstract: One example discloses a near-field wireless communications device, including: a near-field antenna; a near-field noise detector coupled to receive a first set of near-field signals from the near-field antenna; wherein the near-field noise detector is configured to identify a set of attributes of the near-field noise within the first set of near-field signals; a controller configured to generate at least one synchronization signal based on at least one of the attributes of the near-field noise; and a transmitter circuit configured to transmit a second set of near-field signals in response to the synchronization signal.
    Type: Grant
    Filed: August 7, 2020
    Date of Patent: January 17, 2023
    Assignee: NXP B.V.
    Inventors: Anthony Kerselaers, Liesbeth Gommé
  • Patent number: 11557491
    Abstract: A method of forming an assembly is provided. The method includes attaching a packaged semiconductor device to a substrate. An isolation structure is formed and located between the packaged semiconductor device and the substrate. An underfill material is dispensed between the packaged semiconductor device and the substrate. The isolation structure prevents the underfill material from contacting a first conductive connection formed between the packaged semiconductor device and the substrate.
    Type: Grant
    Filed: October 31, 2019
    Date of Patent: January 17, 2023
    Assignee: NXP B.V.
    Inventors: Leo van Gemert, Peter Joseph Hubert Drummen
  • Patent number: 11558018
    Abstract: Integrated circuits, such as power amplifier integrated circuits, are disclosed containing compact-footprint, vertically-integrated capacitor-avalanche diode (AD) structures. In embodiments, the integrated circuit includes a semiconductor substrate, a metal layer system, and a vertically-integrated capacitor-AD structure. The metal layer system includes, in turn, a body of dielectric material in which a plurality of patterned metal layers are located. The vertically-integrated capacitor-AD structure includes a first AD formed, at least in part, by patterned portions of the first patterned metal layer. A first metal-insulator-metal (MIM) capacitor is also formed in the metal layer system and at least partially overlaps with the first AD, as taken along a vertical axis orthogonal to the principal surface of the semiconductor substrate.
    Type: Grant
    Filed: January 29, 2020
    Date of Patent: January 17, 2023
    Assignee: NXP USA, Inc.
    Inventors: Joseph Gerard Schultz, Kevin Kim
  • Patent number: 11558065
    Abstract: One example discloses a reconfigurable analog to digital converter (ADC) device, including: an analog front end (AFE) configured to receive a set of analog input signals and generate a corresponding set of digital output signals; wherein the AFE includes a set of reconfigurable ADC conversion circuits; and a sequencer coupled to the AFE and configured to control the set of reconfigurable ADC conversion circuits with a first AFE channel configuration at a first time and a second AFE channel configuration at a second time.
    Type: Grant
    Filed: January 26, 2021
    Date of Patent: January 17, 2023
    Assignee: NXP B.V.
    Inventors: Jean Cauxuan Le, Carmelo Morello, See-Hoi Wong
  • Patent number: 11557525
    Abstract: A cost-effective process and structure is provided for a thermal dissipation element for semiconductor device packages incorporating antennas that can incorporate RF/EMI shielding from the antenna elements. Certain embodiments provide incorporated antenna element structures as part of the same process. These features are provided using a selectively-plated thermal dissipation structure that is formed to provide shielding around semiconductor device dies that are part of the package. In some embodiments, the thermal dissipation structure is molded to the semiconductor device, thereby permitting a thermally efficient close coupling between a device die requiring thermal dissipation and the dissipation structure itself.
    Type: Grant
    Filed: May 25, 2021
    Date of Patent: January 17, 2023
    Assignee: NXP USA, INC.
    Inventors: Zhiwei Gong, Scott M. Hayes, Michael B. Vincent, Betty Hill-Shan Yeung, Rushik P. Tank, Kabir Mirpuri
  • Patent number: 11555901
    Abstract: Example aspects are directed to operating a SPAD receiver such as may be used in a light detection and ranging (Lidar) system. In one example, the SPAD receiver has SPAD circuitry for multiple photon detections using a single-channel TDC (time-to-digital converter), and such photon detection is quenched after detection so as to establish an effective pre-defined OFF period. In response, the SPAD circuitry is recharged for a subsequent ON period during which the SPAD circuitry is unquenched (or armed) for further photon detection and processing.
    Type: Grant
    Filed: July 27, 2020
    Date of Patent: January 17, 2023
    Assignee: NXP B.V.
    Inventors: Muhammed Bolatkale, Dongjin Son, Maxim Kulesh