Abstract: Various embodiments relate to a mode detector configured to determine a mode of a circuit based upon an attached power source, including: a first latch configured to hold an first input value and output the first held value and an inverse of the first held value; a second latch configured to hold a second input value and output the second held value and an inverse of the second held value; a first output switch connected between a first power source line and a power source output of the mode detector, wherein the first output switch is configured to be controlled by the output of the first latch; a second output switch connected between a second power source line and the power source output of the mode detector, wherein the second output switch is configured to be controlled by the output of the second latch; a first AND gate with a first input and a second input connected to the inverse output of the second latch, wherein the first input is configured to receive a first power on reset signal based upon the f

Abstract: Embodiments of an apparatus and method are disclosed. In an embodiment, a method of multi-link communications involves at a first multi-link device, generating a management frame having reduced neighbor report (RNR) information related to the first multi-link device, and at the first multi-link device, transmitting the management frame having one of the RNR information and a multi-link element (ML IE) or both the RNR information and the ML IE to a second multi-link device.

Abstract: A detection circuit and an integrated circuit. The detection circuit is used for detecting the drift or an open circuit of a first capacitor (C1) on a filtered second power source terminal (220), and the second power source terminal (220) is suitable for acquiring a power source voltage from an unfiltered first power source terminal (210) by means of a first resistor (R1), and is suitable for being coupled to a reference electric potential terminal (230) by means of the first capacitor (C1). The detection circuit comprises a second resistor (R2) and a second capacitor (C2) that are connected in series and coupled between the first power source terminal (210) and the reference electric potential terminal (230), wherein the second resistor (R2) and the second capacitor (C2) have the same time constant as the first resistor (R1) and the first capacitor (C1).

Abstract: Embodiments of an ESD protection device are described. In an embodiment, an ESD protection device includes a first voltage rail electrically connected to a first node, a second voltage rail electrically connected to a second node, and ESD cells connected between the first and second voltage rails and configured to shunt current in response to an ESD pulse received between the first and second nodes. Each of the ESD cells includes clamp circuits electrically connected to the second voltage rail, ballast resistors connected between the first voltage rail and the clamp circuits, where at least some of the ballast resistors are electrically connected to a third voltage rail, a driver circuit connected between the second and third voltage rails and configured to generate a driver signal, and an output stage configured to generate an output signal in response to the driver signal.

Abstract: Embodiments of a method and an apparatus for wireless operations are disclosed. In an embodiment, a method for wireless operations involves announcing, by a first wireless device to a second wireless device, capability parameters, wherein the first wireless device operates according to a first communication protocol and has a first bandwidth capability, and wherein the first wireless device operates according to a second communication protocol and has a second bandwidth capability that is narrower than the first bandwidth capability, receiving, at the second wireless device, the capability parameters announced by the first wireless device, and operating the second wireless device according to the capability parameters announced by the first wireless device.

Abstract: Embodiments for a packaged semiconductor device and methods of making are provided herein, where a packaged semiconductor device includes a package body having a recess in which a pressure sensor is exposed; a polymeric gel within the recess that vertically and laterally surrounds the pressure sensor; and a protection layer including a plurality of beads embedded within a top region of the polymeric gel.

Abstract: Various embodiments relate to an amplitude shift keying (ASK) demodulator for demodulating an input signal, including: a frequency filter configured to receive the input signal, wherein the frequency filter includes adjustable components configured to adjust the frequency response of the frequency filter; a rectifier configured to rectify an output of the frequency filter, wherein the rectifier includes an adjustable current source configured to adjust the current consumption of the rectifier; a reference signal generator configured to produce a reference signal; a current to voltage converter configured to convert the current of the rectified signal to a rectified voltage and to convert the current of the reference signal to a reference voltage; and a comparator configured to compare the rectified voltage to the reference voltage and to produce a demodulated output signal.

Abstract: A first-transceiver for communicating with a second-transceiver is disclosed. The first and second-transceivers are vehicle-access-system transceivers. The transceivers include a cipher-module configured to generate a cipher-code using a cipher key and an input value, an encryption-module configured to generate encrypted-payload-data from payload-data using the cipher-code, a hashing-module configured to hash the payload-data to generate hashed-payload-data using the cipher-code, and a transmitter configured to transmit the encrypted-payload-data and the hashed-payload-data to the second-transceiver. A vehicle including the first-transceiver is also disclosed. Access to one or more systems of the vehicle are controlled in accordance with a validation state.

Abstract: The disclosure relates to a method and system for memory testing to detect memory errors during operation of a memory module. Example embodiments include a method of detecting an error in a memory module (101), the method comprising the sequential steps of: i) receiving (302) a request from a processor executing an application for a read or write operation at a location of the memory module (101) identified by an address; ii) outputting data (304) from, or writing to, the location of the memory module (101); iii) generating (306) by an error detection module (102) a further read request for the location of the memory module (101) identified by the address; iv) receiving (307) at the error detection module (102) an error correction code from the memory module (101) for the location identified by the address; and vi) providing (311) by the error detection module (102) an alert output for the address if the error correction code indicates an error.

Abstract: A communication device receives a physical layer (PHY) protocol data unit (PPDU). The PPDU includes i) a PHY preamble and ii) PHY data portion that includes one or more PHY midambles, and the PHY preamble includes i) an indication of a length of the PPDU, and ii) an indication of a periodicity of PHY midambles in the PHY data portion. The communication device calculates a number of PHY midambles in the PPDU using i) the indication of the length of the PPDU, and ii) the indication of the periodicity of PHY midambles. The communication device calculates a reception time for the PPDU using the calculated number of PHY midambles, and processes the PPDU using the calculated reception time.

Abstract: A thermal increase system may be coupled to a containment structure for containing a load. The system includes a plurality of shelf support structures disposed within a cavity. The plurality of shelf support structures is configured to support a repositionable electrode at a plurality of positions within the cavity. The system includes a first electrode disposed at a first surface of the containment structure, wherein the repositionable electrode is disposed within the containment structure so as to divide the cavity into separate volumes. The system includes a radio frequency signal source electrically connected to one or both of the first electrode and the repositionable electrode. The radio frequency signal source is configured to provide radio frequency energy to either or both of the first electrode and the repositionable electrode.

Abstract: Embodiments of a differential bootstrapped track-and-hold circuit are disclosed. In an embodiment, the differential bootstrapped track-and-hold circuit includes first and second single-ended bootstrapped track-and-hold circuits. Each single-ended bootstrapped track-and-hold circuit includes a sampling switch connected between an input terminal and an output terminal, a sampling capacitor connected to the output terminal, and a dummy sampling switch connected between the input terminal and a dummy output terminal. The sampling switch and the dummy sampling switch are controlled by a bootstrap driver connected to the input terminal.

Abstract: A fringe capacitor comprises a plurality of unidirectional metal layers, wherein an orientation of a preferred direction of each of the unidirectional metal layers is in a same direction. First fingers of the fringe capacitor are formed in a first layer of the unidirectional metal layers, the first fingers being interdigitated and having a direction parallel to the orientation of the preferred direction. Second fingers of the fringe capacitor are formed in a second layer of the unidirectional metal layers, the second fingers being interdigitated and having a direction parallel to the orientation of the preferred direction, the first layer and the second layer separated by at least a layer of not having the orientation of the preferred direction and not having fingers of the fringe capacitor.

Abstract: Various embodiments relate to a method for transmitting a Wi-Fi signal using a channel of 80 MHz or wider, wherein each 80 MHz segment has a tone plan, including: determining that a physical 20 MHz sub-channel overlaps the 80 MHz segment or OFDMA transmission is used for the 80 MHz segment; selecting an alternative 80 MHz tone plan; and transmitting data on the 80 MHz segment using the selected alternative 80 MHz tone plan.

Abstract: Embodiments are directed to a method for determining velocity of an object. The method includes in response to two interleaved chirp sequences being sent towards the object, processing responsive chirps of each of the two interleaved chirp sequences independently from one another to produce respective Doppler-spectrum data sets, and calculating the velocity of the object based on the respective Doppler-spectrum data sets. Each of the interleaved chirp sequences being characterized by a common time spacing between respective chirps of the respective chirp sequence, and each chirp of one of the chirp sequences being offset by an amount of time that is different than the common time spacing.

Abstract: Various embodiments relate to a method for securely comparing a first polynomial represented by a plurality of arithmetic shares and a second compressed polynomial represented by a bitstring where the bits in the bitstring correspond to coefficients of the second polynomial, including: performing a first masked shift of the shares of the coefficients of the first polynomial based upon the start of the interval corresponding to the compressed coefficient of the second polynomial and a modulus value; performing a second masked shift of the shares of the coefficients of the first polynomial based upon the end of the interval corresponding to the compressed coefficient of the second polynomial; bitslicing the most significant bit of the first masked shift of the shares coefficients of the first polynomial; bitslicing the most significant bit of the second masked shift of the shares coefficients of the first polynomial; and combining the first bitsliced bits and the second bitsliced bits using an AND function to p

Abstract: An angular rate sensor includes first, second, third, and fourth proof masses spaced apart from a surface of a substrate, each of the first, second, third, and fourth proof masses being configured to move along first and second transverse axes parallel to the surface of the substrate. A first coupling structure is interposed between and interconnects the first and second proof masses. A second coupling structure is interposed between and interconnects the second and third proof masses. A third coupling structure is interposed between and interconnects the third and fourth proof masses. A fourth coupling structure is interposed between and interconnects the fourth and first proof masses. The first, second, third, and fourth coupling structures are configured to constrain an in-phase motion of adjacent ones of the first, second, third, and fourth proof masses along the first and second transverse axes.

Abstract: A mechanism is provided to remove heat from an integrated circuit (IC) device die by directing heat through a waveguide to a heat sink. The waveguide is mounted on top of a package containing the IC device die. The waveguide is thermally coupled to the IC device die. The waveguide transports the heat to a heat sink coupled to the waveguide and located adjacent to the package on top of a printed circuit board on which the package is mounted. Embodiments provide both thermal dissipation of the generated heat while at the same time maintaining good radio frequency performance of the waveguide.

Abstract: An electronic system comprising a voltage-to-current converter and a proportional-to-absolute-temperature (PTAT) circuit is disclosed. The voltage-to-current converter is configured to receive one of a control voltage, a supply voltage, a scaled-down version of the control voltage, and a scaled-down version of the supply voltage, and generate a set of currents. The PTAT circuit is coupled with the voltage-to-current converter such that each current of the set of currents is one of sourced to the PTAT circuit and sank from the PTAT circuit. Further, the PTAT circuit is configured to receive at least one of the supply voltage and the control voltage, and generate a set of reference voltages. The control voltage is generated based on the set of reference voltages and the supply voltage.

Abstract: A sample and hold circuit configured to sample a current includes an input node to receive the current, a capacitor coupled with a sampling node and a reference voltage node, switch between the input node and the sampling node, a controlled current source coupled to the input node, a current mirror circuit having connections each providing a mirrored current, wherein at least one of said connections provides an output node, and a transistor arrangement. The transistor arrangement includes a control MOSFET in series with a series connected chain of cascaded cells. The control MOSFET and each of said cascaded cells are coupled to the current mirror circuit and each of the cascaded cells includes a pair of MOSFETs arranged to provide a voltage difference including a difference between a gate-source voltage of a first of the pair and a gate-source voltage of a second of the pair.