Abstract: A radio frequency filter (1) comprises an input impedance adaption section (2) and a tank capacitor section (3). Thereby, the capacity of the input impedance adaption section (2) does not comprise a fixed capacitor, it only comprises switchable capacitors. Further, the tank capacitor section (3) does not comprise a fixed capacitor as well it only comprises switchable capacitors. The capacity of the input impedance adaption section (2) can be tuned independent of the tank capacity, section capacity by means of switchable capacitors. Hence, bandwidth and frequency of the radio frequency filter can be modified independent of each other. The imput impendance adaption section (2) is connected in series between the input and output of the filter (1). The tank capacitor section (3) is shunt connected between the input-output series path of the filter (1) and ground.

Abstract: The invention refers to an amplifier (1) comprising a switchable capacitive divider (10) for dividing a supply voltage delivered to the amplifier (1), the switchable capacitive divider being coupled to a coupling circuit (15) via a first wire and a second wire, the coupling circuit determining a connection path between said first and second wire and a first capacitor (C2) and a switchable power circuit (20).

Abstract: An integrated circuit has an inhomogeneous protective layer or coating over a circuit to be protected, and a sensing circuit (80) arranged to sense a first impedance of a part of the protective coating compared to a reference impedance (CO) located on the integrated circuit. The sensing circuit is able to measure a change in the first impedance, e.g. caused by tampering. The sensing circuit has an amplifier (OTA) having a feedback loop, such that the impedance being sensed is in the feedback loop. The sensing circuit can be incorporated in an oscillator circuit (OTA, Comp) so that the frequency depends on the impedance. Where the impedance is a capacitance, sensing electrodes adjacent to the protective layer or coating, form the capacitance. The electrodes can be arranged as selectable interdigitated comb structures, so that the protective layer or coating extends in between the teeth of the comb structures.

Abstract: RF switches are known from the art for selecting an RF signal from a multiple of inputs. For instance a TV-tuner and TV-Front-end can have two or more antenna inputs but are implemented with a relative bad cost performance. The present invention relates to an RF selection switch circuit (200). The switch comprises a first switch (202), a second switch (204) with both an RF input port and a common RF output port a control signal circuitry (206). In a preferred embodiment the switches comprise pin-diodes. The RF output port comprises two transistors (T1, T2), one of which at a time can put the non-selected switch to a low-impedance level in order to minimize signal leakage the common output port.

Abstract: A logic module (400) that is capable of implementing data-path and random logic (command Z in block 42) uses control logic for selectively coupling one or more of the input terminals (10, 12, 14, 16, 18, 40) to the at least one output terminal (20). The control logic comprises a plurality of logic elements (26, 28, 30, 32) arranged to generate a first set of two-input logic functions (f, (a, b)) and a programmable inverter (36) arranged to generate a second set of two-input logic functions, the second set of two-input logic functions being the complement functions of the first set of two-input logic functions. SRAM memory cells (4 bit memory batch (38)) may be used for configuration purposes, realizing a compact logic module or block that is also re-programmable.

Abstract: A data processing system includes processing units for processing data, at least one memory for storing data from the processing units, an interconnect for connecting the processing units and the memory. The processing units request write access to the memory via the interconnect to write data into the memory. At least one arbiter performs interconnect arbitration for the access to the memory from the processing units, wherein interconnect arbitration is performed based on the minimum logic level changes of the interconnect as introduced by the write accesses of the processing units to the memory. If more than one write request is available from different processing units the interconnect arbitration (interconnect access), is granted to that processing unit, whose data to be sent to the memory via the interconnect results in minimum logic level changes to the interconnect. Power dissipation due to switching of logic levels is reduced.

Abstract: A trench MOSFET with drain (8), drift region (10) body (12) and source (14). In order to improve the figure of merit for use of the MOSFET as control and sync FETs, the trench (20) is partially filled with dielectric (24) adjacent to the drift region (10) and a graded doping profile is used in the drift region (10).

Abstract: A method of determining at least one characteristic parameter of a resonant structure (4) comprising the following steps: firstly placing the resonant structure (4) at a location, said location being located in the far field of a first antenna (2) and in the far field of a second antenna (5), and secondly emitting electromagnetic waves (EEW) with different frequencies in a given frequency range by means of the first antenna (2) such that the emitted electromagnetic waves (EEW) are modified by the resonant structure (4) and modified electromagnetic waves (MEW) are achieved, and thirdly determining during a first determining step a first electric power-value being representative of the power associated with the emitted electromagnetic waves (EEW), and fourthly receiving the generated modified electromagnetic waves (MEW) by means of the second antenna (5) and fifthly determining during a second determining step a second electric power-value being representative of the power associated with the received modified

Abstract: A dual or multiple row package (300) is provided which comprises a first plurality of terminals (303, 304, 305) and a second plurality of terminals (306, 307), which first and second plurality of terminals are exposed outside the encapsulation at a first side of the package. The terminals of the first plurality of terminals (303, 304, 305) are arranged in a first row (301), wherein a distance between each pair of adjacent terminals in the first row (301) is greater or equal than a first thresholdvalue. Furthermore, the terminals of the second plurality of terminals (306, 307) are arranged in a second row (302), wherein a distance between each pair of adjacent terminals in the second row (302) is greater or equal than a second threshold and a distance between the first row (301) and the second row (302) is smaller than at least the first threshold value.

Abstract: An electronic device is provided with at least one functional unit (HB) performing a processing, wherein the functional unit (HB) receives a supply current (Isupply). A supply current monitor (SCM) is provided for monitoring the supply current (Isupply) to determine an average supply current (Iavg). A characterization unit (CU) is provided for determining a first relation between the averaged supply current (Iavg) and an operation frequency of the functional unit and/or for determining a second relation between a workload of the functional unit (HB) and the average supply current (Iavg) of the functional unit (HB). Furthermore, a slope calculation unit (SCU) is provided for determining the slope of the first and/or second relation. The operation of the functional unit (HB) is controlled according to the results of the slope calculation unit (SCU).

Abstract: An electronic device (100) comprises a substrate (101), a first electrode (102) formed at least partially on the substrate (101), a second electrode (103) formed at least partially on the substrate (101), a convertible structure (104) connected between the first electrode (102) and the second electrode (103), and a spacer element (105) connected between the first electrode (102) and the second electrode (103) and adapted for spacing the convertible structure (104) with regard to a surface of the substrate (101)

Abstract: An electronic device is provided with a high-voltage tolerant circuit. The high-voltage tolerant circuit comprises an input terminal for receiving an input signal (VIN), a first node (A) and a second node (B), wherein the second node (B) is coupled to an input of a receiver (R). The high-voltage tolerant circuit furthermore comprises a first NMOS transistor (N1) and a first PMOS transistor (P1) coupled in parallel between the input terminal and the second node (B). Furthermore, a second PMOS transistor (P2) is coupled between the input terminal and node A and a second NMOS transistor is coupled with one of its terminals to the first node. The gate of the first NMOS transistor (N2) is coupled to a supply voltage (VDDE). The gate of the first PMOS transistor (P1) is coupled to the first node (A). The gate of the second NMOS transistor (N2) and the gate of the second PMOS transistor (P2) are coupled to the supply voltage (VDDE).

Abstract: The present invention relates to a display system which comprises an LCD display panel (DP) for displaying video signals from a video source (VS), and a backlighting unit (BL) for backlighting the display panel (DP). Furthermore, a luminance analyzing unit (LA) is provided for analyzing the luminance of at least parts of the video signals from the video source (VS). A backlighting control unit (BC) is provided for controlling the operation of the backlighting unit (BL) based on at least a first or second color temperature of a white-point setting according to the analyzing results of the luminance analyzing unit (LA).

Abstract: The invention relates to an ESD protection device comprising: a first contact (10) and a second contact (20), and an electrical node (12); a bipolar transistor (6) having a base, an emitter, and a collector, the base and emitter forming a base-emitter junction, the base and collector forming a base-collector junction, the emitter being connected to the first contact (10), the collector being connected to the second contact (20), the base being connect to the electrical node (12); a first diode (1) connected between the electrical node (12) and the first contact (10), the first diode (1) comprising a first junction arranged in the same direction as the base-emitter junction, and—a second diode (2) connected between the electrical node (12) and the second contact (20), in anti-series with the first diode (1) on a path from the first contact (10) to the second contact (20), the second diode (2) comprising a second junction arranged in the same direction as the base-collector junction, wherein the bipolar transis

Abstract: A device (100) for processing data, the device (100) comprising a plurality of signal paths (130, 140, 150) each receiving an identical analog input signal (104), at least one signal conditioning unit (101 to 103) in at least one of the plurality of signal paths (130, 140, 150), wherein each signal conditioning unit (101 to 103) is adapted for generating a respective analog intermediate signal (105 to 107) by manipulating a property, particularly an amplitude, of the analog input signal (104), and a plurality of analog to digital converting units (108 to 110) each of which being assigned to a corresponding one of the plurality of signal paths (130, 140, 150) and being supplied with the analog input signal (104) or a respective analog intermediate signal (105 to 107), wherein each of the plurality of analog to digital converting units (108 to 110) is adapted for generating a respective digital intermediate signal (111 to 113) based on the respective analog intermediate signal (105 to 107) or based on the analo

Abstract: In a method of transmitting data, a low or high frequency transponder (4) receives a first data stream (12) via a field emitted by a reader (1), decodes the first data stream (12) utilizing an internal clock signal (13) generated by the transponder (4), and generates and emits a second data stream (14) to the reader (1) in response to the first data stream (12). The second data stream (14) is generated and transmitted utilizing a clock information transmitted via the field emitted by the reader (1).

Abstract: A resonant converter comprises switching circuitry (1) for supplying pulses, at a controllable frequency, to a resonant circuit so as to power the primary circuit (3, 12) of a transformer (4). The secondary winding (5a, 5b) of the transformer (4) delivers an AC signal which is rectified and then produces a load current. On the primary side, the converter has a resistor (13) for deriving a first electrical signal representative of the current in the primary circuit (3, 12), and an auxiliary winding (14) which is closely coupled to the secondary winding (5a, 5b) and across which an auxiliary voltage is induced as a consequence of the close coupling of the winding (14) to the secondary winding (5a, 5b). A resistor/capacitor combination (16, 17) integrates the auxiliary voltage with respect to time to derive a second electrical signal.

Abstract: The invention relates to multi-phase clock system for receiving a plurality of clock signals (CLKo-n) comprising actual time events (aTE) defining different clock phases, the clock signals all having a same clock frequency but different clock phases, the system further arranged for receiving a reference clock signal (REFCLK) for providing reference time events (rTE) for the plurality of clock signals (CLKo-n), the reference clock signal (REFCLK) having a reference frequency different from the clock frequency, the reference frequency being selected such that each one of the subsequent reference time events (rTE) coincides with a desired time event (dTE) for a single one of the plurality of clock signals (CLKo-n).

Abstract: An integrated circuit comprises a matrix (10) of programmable cells (100). Each particular one of the programmable cells (100) comprises a programmable logic circuit (22) and a bank (24) of routing multiplexers (25a-d). Each routing multiplexer (25a-d) in the bank (24) has a set of inputs connected to connections selected from a group consisting of connections to an output of the programmable logic circuit (22) and connections dedicated to outputs of routing multiplexers (25a-d) in further ones of the programmable cells (100) other than the particular one of the programmable cells (100). The further ones of the programmable cells (100) the inputs of the routing multiplexer (25a-d) in the bank (24) are connected to are positioned relative to the particular one of the programmable cells (100) in the matrix (10) in neighboring cells (100) of the particular one of the programmable cells (100) and in cells (100) beyond the neighboring cells (100).

Abstract: An administrator node (130) adjusts a trustworthy-measure associated with nodes (110) that are suspected of unauthorized modifications of content material. The original provider of the content material to a network binds an identifying code to it. Upon receiving the material from a source node (110), a target node (120) computes an associated code for the received material. If the computed code and the identifying code differ, the material is determined to be modified, and a discrepancy report is submitted to the administrator node (130). The administrator node (130) effects a penalty against the root source if the modification is confirmed; or against the target node (120) if the discrepancy report is unfounded. The penalties include downgrading of the trustworthiness-measure associated with each node, and these trustworthiness-measures are available for use by potential target nodes in their selection of preferred source nodes.