Abstract: The present invention relates to a method of receiving a multimedia signal in a communication apparatus, said multimedia signal comprising at least a sequence of video frames (VF) and a sequence of audio frames (AF) associated therewith. Said method comprises the steps of: processing (21) and displaying (25) the sequence of audio frames and the sequence of video frames,—buffering (24) audio frames in order to delay them, detecting (22) if the face of a talking person is included in a video frame to be displayed, selecting (23) a first display mode (m1) in which audio frames are delayed by the buffering step in such a way that the sequence of audio frames and the sequence of video frames are synchronized, and a second display mode (m2) in which the sequence of audio frames and the sequence of video frames are displayed without delaying the audio frames, the first display mode being selected if a face has been detected and the second display mode being selected otherwise.

Abstract: A method of reading data (DAT1 . . . DAT4) from transponders (T1 . . . T4) by means of a reader device (RD) during a number (N) of time slots (TS) is disclosed, wherein the seizure of said time slots (TS) by the transponders (T1 . . . T4) is observed in both the reader device (RD) and the transponders (T1 . . . T4). A reorganization (REORG) is performed in dependence on said seizure, wherein both the reader device (RD) and the transponders (T1 . . . T4) choose a new number (N) of time slots (TS). In addition, the transponders (T1 . . . T4) select one of the new time slots (TS) in which to send data (DAT1 . . . DAT4) back to the reader device (RD) so as to adapt the system's capacity to the real demands. Preferably, said reorganization (REORG) takes place without communication between the reader device (RD) and the transponders (T1 . . . T4). The invention further relates to a transponder (T1 . . . T4) and to a reader device (RD) for implementing the inventive method.

Abstract: The present invention relates to an integrated circuit (30) comprising a logic circuit (42) and reception means (34) for receiving external signals and for transmitting said received external signals to said logic circuit (42), and it relates to a device coupled to such an integrated circuit and to methods for manufacturing and operating such an integrated circuit and for transmitting control data to a device.

Abstract: In the manufacture of electronic devices (22, 22?), e.g. discrete semiconductor power devices or ICs, a reversible bonding tool (10) is used having a bonding tip or wedge (1, 2) at each of its opposite ends (11, 12). After extensive use of the wedge-tip (1) at one end (11) for bonding wires (21), the tip (1) is worn somewhat. Instead of needing to replace the bond tool as in the prior art, the tool (10) in accordance with the invention is then reversed to use the wedge-tip (2) at the opposite end (12) for bonding further wires (20?). Thus, a cost saving is achieved with regard to tool material.

Abstract: An electronic device for generating an electric oscillating signal is described based on a micro-electromechanical system (MEMS). The electronic device typically comprises a substrate (104) a moveable element (102) which is moveable with respect to the substrate (104) and an actuating means and a sensor. The actuating means is used to induce vibration of the moveable element (102) and comprises two inductive elements, a first one provided fixed to the substrate (104) and a second one provided fixed to the moveable element (102). The induced vibration of the moveable element (102) is sensed using the sensor and converted into an electric oscillating signal. The signal may be amplified and used for at least partly powering the actuating means, such that an oscillating signal at a stable resonance frequency and with a fixed amplitude can be obtained. The different components are highly integratable on chip.

Abstract: An electronic device comprising at least one input/output circuit (10) in a first supply voltage domain (VDD, GND) is provided. The electronic device furthermore comprises a buffer (INV) which is coupled to the input/output circuit for driving an input of the input/output circuit (10). The buffer comprises a first and second switch (T1, T2; T4, T5). The buffer is arranged in a second supply voltage domain (VDD1, GND1). Furthermore, a control circuit is coupled to the buffer for controlling the first and second switch (T1, T2; T4, T5) such that during a transition of an input signal of the input/output circuit (10) both switches (T1, T2; T4, T5) are temporarily kept in a conducting state and a crowbar current flows through the buffer (INV).

Abstract: A non-volatile memory device on a semiconductor substrate having a semiconductor surface layer (2) comprises a source region (12,S), a drain region (12,D), a channel region (CO), a memory element (ME), and a gate (G). The channel region (CO) extends in a first direction (X) between the source region (12,S) and the drain region (12,D). The gate (G) is disposed near the channel region (CO) and the memory element (ME) is disposed in between the channel region (CO) and the gate. The channel region is disposed within a beam-shaped semiconductor layer (4), with the beam-shaped semiconductor layer (4a, 4b, 4c, 4d) extending in the first direction (X) between the source (12,S) and drain (12,D) regions and having lateral surfaces (4a, 4b, 4c, 4d) extending parallel to the first direction (X).

Abstract: The apparatus of the present invention improves performance of computing systems by enabling a multi-core or multi-processor system to deterministically identify cache memory (100) blocks that are ripe for victimization and also prevent victimization of memory blocks that will be needed in the immediate future. To achieve these goals, the system has a FIFO with schedule information available in the form of Estimated Production Time (EPT) (102) and Estimated Consumption Time (ECT) (104) counters to make suitable pre-fetch and write-back decisions so that data transmission is overlapped with processor execution.

Abstract: A multi-port cache memory (200) comprising a plurality of input ports (201, 203) for inputting a plurality of addresses, at least part of each address indexing a plurality of ways; a plurality of output ports (227, 299) for outputting data associated with each of said plurality of addresses; a plurality of memory blocks (219a, 219b, 219c) for storing said plurality of ways, each memory block comprising a single input port (217a, 217b, 217c, 217d) and storing said ways; means (209, 215, 223, 225) for selecting one of said plurality of ways such that data of said selected way is output on an associated output port (227, 229) of said cache memory (200); a predictor (211) for predicting which plurality of ways will be indexed by each of said plurality of addresses; and means (213a, 213b, 213c, 213d) for indexing said plurality of ways based on the predicted ways.

Abstract: Disclosed is a method and apparatus for managing transmit requests among a plurality of co-located transmitting devices each associated with a wireless transmitting protocol. The method comprises the steps of determining the cost associated with each of the transmit requests, wherein the cost is associated with the cost of granting the request and the cost of rejecting the request, granting the request associated with the lowest cost, and rejecting all other requests. In another aspect of the invention, the method comprises the step of determining whether the lowest cost is acceptable and rejecting the request associated with the lowest cost when the lowest cost is unacceptable.

Abstract: An inflatable loudspeaker enclosure (1, 1?), comprising at least two speakers (4) and an inflatable body (2), wherein the speakers (4) are embedded in the body (2) in such a way that a relative movement of the speakers (4) in relation to each other is enabled. According to a preferred embodiment of the invention, each speaker (4) comprises an edge (5) for fixing the speaker (4) to the body (2). In a further preferred embodiment each speaker (4) is attached to a frame (15) which is embedded in the body (2) in airtight manner.

Abstract: A non-volatile main memory (10) comprises a plurality of physical blocks of memory locations. Pointing information (112a-c, 114a-c) is stored in the main memory (10), the pointing information comprising pointers (112a-c) to used blocks in use for particular functions and pointers (114a-c) to free blocks that are free for future use for the particular functions. The free blocks to replace selected ones of the used blocks. After this happens an updated version of the pointing information may be written to the main memory only after using at least two of the free blocks as replacements. On start up at least one of the pointers (114a-c) to the free blocks is used to access at least one of the free blocks and to determining whether the accessed free block has been used as a replacement for a particular one of the used blocks. If so, the free block is used instead of the particular one of the used blocks.

Abstract: Silicon wafers and the like are cleaned using new scrubber-type apparatus in which measures are taken to compensate for differential cleaning of the central region of the wafer by: using rotary brushes having one or more non-contact portions arranged in the section thereof that faces the central region of the substrate, or toggling the relative position of the wafer and the rotary brushes, or directing cleaning fluid(s) preferentially towards the central region of the wafer. Another aspect of the invention provides scrubber-type cleaning apparatus in which the rotary brushes are replaced by rollers (110). A web of cleaning material (116) is interposed between each roller and the substrate. Various different webs of cleaning material may be used, e.g. a length of tissue, a continuous loop of cleaning material whose surface is reconditioned on each cleaning pass, adhesive material provided on a carrier tape, etc.

Abstract: A die package (72) for a semiconductor die (20). A plurality of the die packages (72) are formed on a single carrier (10) by applying a body (55) of molding compound across a carrier (10) with an air cavity (70) defined in the molding compound about each of a plurality of device regions (12) of the carrier (10). After a semiconductor die (20) is attached inside the air cavity (70) of each device region (12) and electrically connected with at least one contact pad (14, 16, 18), a cover (68) is applied to close all of the air cavities (70). Following singulation, each semiconductor die (20) is located inside the sealed air cavity (70) of one die package (72). The molding compound of each die package (72) may be locked against movement relative to the device region (12) of the carrier (10) by locking features (30, 38, 48, 50).

Abstract: A vertically oriented self terminating discrete trench MOS device (1) that includes a cylindrical drift region (18) that extend downward from a surface region to a substrate (11) and a dielectric region (20) that exponentially tapers outward from the cylindrical drift region as the drift region approaches the substrate.

Abstract: A plurality of integrated circuits that are used in an electronic circuit have functional interconnections and dedicated test connections. The integrated circuits receive and transmit synchronization information, such as clock signals from one integrated circuit to another successively through the chain. This permits a high-test speed. Preferably the synchronization information is serialized with test data, test results and/or commands. Preferably, the bit rate between successive integrated circuits in the chain is programmable by means of commands transmitted through the chain. Thus, different bit rates may be at different locations along the chain to reduce the delay occurred by the synchronization signals along the chain.

Abstract: A dc-to-dc converter has two field effect transistors connected in series between an input terminal and a ground terminal. Adjustment of the dead time when both transistors are off is carried out by providing Kelvin feedback connections directly across the drain and source of one or both of the transistors, so bypassing signal line resistance and inductances.

Abstract: Consistent with an example embodiment, there is a method is for powering an integrated circuit. An integrated circuit comprises a chip within a package assembly, the chip includes a plurality of logic circuits each having at least one power input which should not receive a power voltage exceeding a predetermined maximum operating voltage. The method comprises measuring a power voltage supplied to the integrated circuit directly within the chip at the power input of at least one logic circuit. The power voltage is regulated such that the voltage supplied to the power input of at least one logic circuit of the chip is equal to the predetermined maximum operating voltage of this logic circuit.

Abstract: To improve the recognition of the validity of coded control information that is transmitted, together with associated useful data, as a data signal and that is decoded at the receiver by means of a Viterbi decoder (VDCOD), it is proposed that at least an end section of the received, convolution-coded control information is prefixed to this same information, the length of the end section being at least that of the convolution-coded tail bit-sequence, and the information that has been assembled in this way being fed to the Viterbi decoder to allow the convolution-coded control information to be decoded.

Abstract: A bias circuit for use in bandgap voltage reference circuits and temperature sensors comprises a pair of transistors (Q, Q2), the first of which (Q1) is arranged to be biased at an emitter current lbias, and the second of which (Q2) is arranged to be biased at an emitter current of m.lbias. The circuit is arranged such that the difference between the base-emitter voltages of the transistors is generated in part across a first resistance means having a value Rbias and in use carrying a bias current equal to lbias and in part across a second resistance means of value substantially equal to Rbias/m and in use carrying a current equal to the base current of the second transistor. This results in use in a bias current Ibias which, when used to bias a substrate bipolar transistor via its emitter, produces a collector current therefrom which is substantially PTAT and a base-emitter voltage which is substantially independent of the forward current gain of the substrate bipolar transistor.