Abstract: The present invention enables the user to measure process line shortening (PLS) on an overlay tool. In an example embodiment (900), to obtain the PLS, the user applies a method to determine the misalignment (MA) of a composite image on a substrate (940a), from the composite image the user may determine the total line (940b) shortening (TLS) and the equipment line (940c) shortening (ELS). The process line shortening (PLS) is determined (940d) as a function of TLS and ELS.

Abstract: Interchangeable high band low-noise-amplifiers (LNAs) and low band low-noise-amplifiers (LNAs) and related methods are disclosed that greatly enhance the efficiency of designing handsets for different combinations of frequency bands. The input signals to particular pins on a receiver or transceiver integrated circuit (IC) are swappable such that multiple frequency bands can be input to the same input pins thereby allowing for simplified system design. Efficient programmable techniques are also disclosed for controlling a swap mode within communication ICs. These interchangeable or band swappable input paths, for example, can be utilized to allow interchangeability between high band (PCS, DCS) and low band (GSM, E-GSM) inputs for cellular communications.

Abstract: The invention relates to a one-time programmable memory device. In order to make such a memory device particular simple and reliable, it is proposed that the device comprises a MOS selection transistor T1 and a MOS memory transistor T2 connected in series between a voltage supply line BL and ground Gnd. The device further comprises programming means for applying predetermined voltages Vsel, Vctrl, Vprog to the gate of the selection transistor T1, to the gate of the memory transistor T2 and to the voltage supply line BL. The applied voltages Vsel, Vctrl, Vprog are selected such that they force the memory transistor T2 into a snap-back mode resulting in a current thermally damaging the drain junction of the memory transistor T2. The invention relates equally to a corresponding method for programming a one time programmable memory.

Abstract: A method of manufacturing a trench-gate semiconductor device (1), the method including forming trenches (20) in a semiconductor body (10) in an active transistor cell area of the device, the trenches (20) each having a trench bottom and trench sidewalls, and providing silicon oxide gate insulation (21) in the trenches such that the gate insulation (33) at the trench bottoms is thicker than the gate insulation (21) at the trench sidewalls in order to reduce the gate-drain capacitance of the device.

Abstract: A method for a predistortion linearization of a branched signal for a RF amplifier, comprising supplying a branched signal to at least one input terminal (2); distributing power of the input signal present on at least one input terminal (2) to a plurality of parallel branch-circuits (16, 18, 20) as a branched signals by a power distributing circuit (4); controlling a phase parameter and an amplitude parameter of the branched signals by at least one nonlinear branch-circuit (18, 20); controlling a phase parameter and an amplitude parameter of the branched signals by at least one linear branch-circuit (16); combining output branched signals of at least one nonlinear branch circuit (18, 20) with the output branched signals of at least one linear branch circuit (16) by a power combining circuit (12); providing an output branched signal of the power combining circuit (12) on at least one output terminal (14).

Abstract: The present invention relates to a method using windows of data, a window (w) comprising data to be written and to be read and having a size. It is characterized in that it comprises:* A step of writing a current window of data into a unique buffer (BUF) in a first address direction, said first address direction being at an opposite direction from an address direction of the writing of a preceding window of data, said writing of said current window beginning at an address where no data of the preceding window of data have been written, said buffer (BUF) having a length greater than the maximum size of the windows of data, and* A step of reading the data of said preceding window of data from said unique buffer (BUF), from a reading address equal to a last written address of the same preceding window of data, said reading being made simultaneously to said writing of the current window of data and in the same first address direction.

Abstract: The invention provides for a method and related device and control program for use in decoding executable code in a processing system, for example run-time operating system, including bit-shuffling code at run-time, and including the steps of dividing the code into a plurality of sub-portions, identifying sub-portions of the code that can be bit-shuffled prior to the said run-time and bit-shuffling the said identified sub-portions prior to run-time so as to reduce the bit-shuffling required at run-time.

Abstract: A trench-gate vertical power transistor in which the trench-gates (11) are parallel stripes which extend across the active area (100). Source regions (13) and ruggedness regions (15) extend to a source contact surface as alternating stripe areas having a width perpendicular to and fully between each two adjacent parallel stripe trench-gates (11). The ruggedness regions (15) are more heavily doped than the source regions and this enables an increased length of the source regions with a consequent reduction in specific resistance of the transistor. For example, the mesa width (13,15) and the trench-gate (11) width may both be about 0.4 ?m, the ruggedness region (15) length may be about 1 ?m and the source region (13) length may be about 20 ?m. The doping concentration of the p type ruggedness regions (15) may be approximately 10 times greater than the doping concentration of the n type regions (13), for example about 1021 cm?3 and about 1020 cm?3 respectively.

Abstract: A signal processing unit is described relates to a communication system by radio waves with frequency modulation comprising a signal processing unit, a transmission stage for transmitting a transmission signal in response to a modulated control signal and in response to a first frequency reference signal, a modulator connected between the processing unit and the transmission stage for forming the modulated control signal in response to an output signal of the processing device and in response to a second frequency reference signal and means for providing the first frequency signal to the transmission stage and for providing the second frequency reference signal to the modulator wherein the first and second frequency reference signal are derived from a signal oscillator.

Abstract: A control unit, for controlling a threshold voltage of a circuit unit having transistor devices, includes a reference circuit and a measuring unit. The measuring unit is configured to measure a threshold voltage of at least one sensing transistor of the circuit unit, and to measure a threshold voltage of at least one reference transistor of the reference circuit. A differential voltage generator is configured to generate a differential voltage from outputs of the measuring unit and a bulk connection of the transistor devices in the circuit unit to which the differential voltage is fed as a biasing voltage.

Abstract: A wireless communication device is disclosed that provides a sidetone to the device user. The device converts an outbound analog audio signal to an outbound audio bitstream from which a sidetone bitstream is extracted. The device also converts an inbound digital audio signal to an inbound audio bitstream. A filter in the device both adds the sidetone bitstream to the inbound audio bitstream and filters the resultant added bitstreams to provide an analog audio signal with sidetone.

Abstract: Power conversion circuits often consist of several MOSFETs operating in parallel. Due to thermal cycling and mechanical operations. MOSFETs or the respective electric connections of the MOSFETs may fail. For certain implementations, a diagnosis circuit for a plurality of parallel MOSFETs predicts or determines a possible failure on the basis of at least one of temperatures of the MOSFETs or gate voltages of the MOSFETs. In some applications, the MOSFETs are monitored to facilitate early determination of failures of the MOSFETs.

Abstract: Consistent with an example embodiment, there is dual residue pipelined AD converter comprising a cascade of, preferably balanced, switched capacitor dual residue converter stages for producing from first and second residue input signals one or more digital bits and first and second residue output signals for application to the next stage in the cascade. Preferably the first and second residue input signals charge input capacitors whose charge is subsequently transferred to output capacitors by means of operational amplifiers. The switched capacitor architecture allows compensating for DC-offset voltages of the operational amplifiers. The switched capacitor architecture also allows the implementation of 1.5 bit converter stages.

Abstract: An automatic gain control circuit has a gain determination circuit (B2) which determines a first gain factor (g), and a first gain controller (B3) which controls an amplitude of an input signal (S1) with the first gain factor (g) to supply a gain controlled signal (S3). A processing circuit (B1; B1, B11) with a predetermined limited dynamic range processes the gain controlled (S3) to obtain an output signal (S4; S2). The automatic gain control circuit further comprises a compensation circuit (B5) which determines a second gain factor (dg) based on the first gain factor (g) and input parameters (DL, TR, DV) which define a time variation of the second gain factor (dg), and a second gain controller (B1; B10) which receives the second gain factor (dg) to obtain a compensated output signal (S2) that is substantially compensated for an amplitude change of the gain controlled signal (S3) due to a change of the first gain factor (g).

Abstract: Consistent with an example embodiment, a method of manufacturing a semiconductor device comprises MOS transistors having gate electrodes formed in a number of metal layers deposited upon one another. Active silicon regions having a layer of a gate dielectric and field-isolation regions insulating these regions from each other are formed in a silicon body. Then, a layer of a first metal is deposited in which locally, in a part of the active regions, nitrogen is introduced. On the layer of the first metal, a layer of a second metal is then deposited, after which the gate electrodes are etched in the metal layers. Before nitrogen is introduced into the first metal layer, an auxiliary layer of a third metal permeable to nitrogen is deposited an the first metal layer. Thus, the first metal layer can be nitrided locally without the risk of damaging the underlying gate dielectric.

Abstract: A method of despreading GPS spread spectrum signals containing pseudorandom noise (PRN) code sequences and received by a GPS receiver (24) is disclosed together with a GPS receiver (24) and a mobile communications device (MS1) (especially a mobile cellular telephone) for the same. The method comprises the steps of providing Doppler information relating to an estimate of the variation in Doppler shift as observed on the target signal by the GPS receiver and which is attributable to the motion of the GPS satellite; and correlating the target signal with a reference signal containing corresponding PRN code sequences, wherein, in the course of a single dwell, the correlation is modified as a function of the Doppler information.

Abstract: A method of operating a radio-frequency (RF) circuitry and a signal-processing circuitry in a mobile telephone apparatus includes operating the RF circuitry during a first time period. During the first period, the RF circuitry generates a set of data from an RF signal received by the mobile telephone apparatus. The method further includes storing the set of data in a storage device. The method also includes operating the signal-processing circuitry during a second time period to process the set of data.

Abstract: A random number generator includes a chain of pairs of D-type flip-flops 205, 215 . . . having D and L inputs, a chain of substantially identical cascaded upper buffers 210,220 . . . each having a predetermined delay d1 and respective output taps. There is a chain of substantially identical cascaded lower buffers 240,260 . . . each having a predetermined delay d2, and respective output taps, wherein d1?d2. A first one of the pair of D-type flip flops 205 has its D and L inputs connected to a respective output tap of one of the upper buffers 210 and a respective output tap of one of the lower buffers 240, and a second one of the pair of D-type flip flops has its D and L inputs connected to a respective output tap of one of the lower buffers 260 and a respective output of one of the upper buffers 215. The common clock input 201 is connected to the first inputs of both the cascaded upper buffers and the cascaded lower buffers 210, 220 . . . and 240, 260 . . . A metastability detector 275,280 285,290,295 . . .

Abstract: A method to obtain configuration data for a data processing apparatus by calculating (110) a time interval between the commencement of a mode (104) and a subsequent event (108). The calculated time interval is then compared (112) with one or more reference values (114). The result of the comparison is used to derive configuration data (116). The method may be further refined by including a calibration stage to reduce the error in the calculated time interval, thereby allowing comparison with a larger set of reference values (114), which in turn permits more configuration data to be derived from the calculated time interval.

Abstract: A communication system such as a telephone system has at least a base station and a communication device to communicate with the base station, the communication device comprises an RF power amplifier having an RF output for coupling to an antenna and an RF output power control input, a power supply having a power supply terminal, a control input and a supply output coupled to the RF output power control input for controlling an RF output power on the RF output in dependence on a signal on the control input of the power supply, a data receiver means for coupling to the antenna, the data receiver means having a data output for providing data received from the base station which represents information about said RF output power, and a table means containing a listing of possible power supply control input values related to possible RF output power values, the table means having a table selection input coupled to the data output of the data receiver means and a table output coupled to the control input of the pow