Abstract: In a device for detecting the temperature of an oscillator crystal 2, arranged on a carrier, in particular in a mobile radio apparatus, the detected temperature should be as exact as possible a replica of the temperature to which the oscillator crystal 2 is subjected. For this purpose, a temperature sensor 7 is arranged on the carrier 1 in such a way that it is subjected to the same ambient temperature as the oscillator crystal 2 or the oscillator-crystal housing 2?. The temperature sensor 7 and the oscillator crystal 2 are located so as to be electrically parallel.

Abstract: The invention relates to a resonator filter structure (10) for radio frequency (RF) filters, especially a bulk acoustic wave (BAW) filter structure. According to the invention, a resonator filter structure (10) is constructed with a BAW lattice filter section (20), in which all of the BAW resonator elements (20-1, 20-2, 20-3, 20-4) within the BAW lattice filter section (20) have substantially equal resonance frequencies. According to the invention, there are parallel capacitances (30-1, 30-2) connected in parallel to the BAW resonators (20-2, 20-3) of one branch type of the BAW lattice filter section (20). Thus, anti-resonance frequency of the respective BAW resonator (20-2, 20-3) is tuned. That results in a very narrow passband which corresponds approximately to the difference in anti-resonance frequencies between diagonal and horizontal branches of the lattice filter section (20). The parallel capacitances (30-1, 30-2) are used to tune the bandwidth: the smaller the capacitance, the smaller the bandwidth.

Abstract: A television tuner comprises a tunable bandpass filter (4) for selecting a desired input channel with an image canceling capacitor (C8) for rejecting the image frequency of the desired input channel. In order to avoid the necessity of different printed circuit boards for NTSC-type television tuners and for PAL-type television tuners, the image canceling capacitor (C8) is made of first (8) and second (10) traces of the printed circuit board while a third trace (13) is connected to the second trace (10) by a jumper (15) only in case of a PAL-type tuner.

Abstract: The invention relates to a mixer circuit comprising an input node for receiving an input signal, a first output node 202, and a second output node 203, voltage to current conversion means and switching means operatively coupled to each other and to the input node, the first output node and the second output node to generate a mixed input signal at the first output node and the second output node in response to an oscillator signal. In an embodiment the voltage to current conversion means comprises a first and a second voltage to current converter, implemented as N-MOSFETs M2 and M3, with their gates connected to the input node. The drain of M2 is connected to the first output node 202, while the drain of the M3 is connected to the second output node M3. The source of M2 is connected to the switching node 221, while the source of M3 is connected to the second switching node 222.

Abstract: In a transceiver comprising a time-division-duplex (TDD) of transmit and receive functions, the characteristics of unwanted image signal energy being transmitted from the transceiver are determined, and thereafter feedback is provided to the transmitter to reduce this unwanted image signal energy. The image signal energy is measured by the receiver component of the transceiver and fed back to the transmitter component of the transceiver. The transmitter component uses the fed back information to adjust the gain and or phase relationship between the quadrature signals that are subsequently quadrature-phase modulated and transmitted. A variety of techniques can be employed to allow the image signal energy to be measured directly by the receiver component. The phase modulation signals at the transmitter can be interchanged, so that the unwanted image signal energy is transmitted in the sideband of the intended signal.

Abstract: The present invention relates to a suppression device for an arrangement for the transmission of audio signals, in particular uttered speech, having: an echo reduction unit (4), which is arranged between an input channel (1) for receiving an input audio signal (A1) coming from a remote end and an output channel (5) for outputting an output audio signal (A2), for suppressing an echo signal contained in the output audio signal (A2), a speech activity detection unit (7) for detecting a speech signal contained in the input audio signal (A1), and, a control unit (6) for setting an echo suppression factor(s) of the echo reduction unit (4) for echo suppression.

Abstract: The present invention relates to a communicating data system comprising devices (11, 12, 13, 14) for routing said data that are interconnected by communication links, the data being transmitted in packets and a packet comprising a header. A transmitting part of a first routing device (12) comprises first storage means suitable for storing a value of at least one parameter from said header and for transmitting a coded value corresponding thereto, and first entropy coding compression means which are suitable for recoding the uncoded value, the recoded value being stored instead of the coded value after the latter is transmitted along a communication link (15).

Abstract: A random number generator includes a flip-flop, and a pair of independent free-running oscillators having a respective set of 4 switches controlled with a non-inverted and inverted output of the flip-flop. An output from each of the oscillators is fed back to their respective input via a delay device. The pair of oscillators each has a feedback loop switch, and a pair of cross gate switches, each of which respectively connects an input signal of one oscillator to an output of another oscillator of the pair of oscillators. When the feedback loop switches are open and the cross gate switches are closed, the pair of oscillators forming a flip-flop with positive feedback resolves to a logic state that in a metastable way, producing an unpredictable (random) logic signal.

Abstract: A traveling-wave amplifier includes amplifiers coupled anti-parallel to transmission lines. Phase(s) of the amplifiers provide phase matching, which may additionally or alternately be provided by couplers or spatial offset of the amplifiers and couplers. The traveling-wave amplifier provides compensation for the losses of the transmission lines, amplification of the signals and isolation between input and output by coupling the amplifiers to the transmission lines anti-parallel.

Abstract: A receiver for receiving an MPEG encrypted transport stream and outputting audio and video signals comprising: a decryptor adapted to receive and decrypt the encrypted transport stream; a de-multiplexer adapted to convert the decrypted transport stream to audio and video elementary streams and to change the values in presentation time stamp and decoding time stamp fields of each packet of the audio and elementary streams to match the time of a receiver record clock; a storage sub-system adapted to store the audio and the video elementary streams and to change the values in the presentation time stamp and decoding time stamp fields of each header of the audio and video elementary streams to compensate for the amount of time the audio and video elementary streams are stored; and audio and video decoders to decode the audio and video elementary streams respectively.

Abstract: A display apparatus comprises a signal converter (SC) which converts input text information (IT) and interlaced input video information (IV) with a number of video lines (Li) in a video field (Fi) into a display signal (DS) which comprises display text (Ti) and display video (Vi). An addressing circuit (AD) addresses a display screen (DSC) of the display apparatus in successive non-interlaced display fields (Fi) which have a duration substantially equal to the video field (Fi) and a number of display lines (DLi) which is substantially twice the number of video lines (Li). The signal converter (SC) has an output to supply the display signal (DS) in which the display video (Vi) is present on odd or even display lines (DLi) only, in respective successive display fields (Fi), and in which the display text (Ti) is present on same display lines (DLi) of the successive display fields (Fi).

Abstract: The invention relates to a method for connecting a connecting surface of a first silicon wafer [WA1] with a connecting surface of a second silicon wafer [WA2] so as to form an insulated cavity after assembly, at least one of the two silicon wafers [WA] including at least one functional area [DA] intended to be within the cavity. The method according to the invention includes a step [PLTS] of depositing alloy soldering bumps [PLTC] on the connecting surface of the first silicon wafer [WA1], said bumps [PLTC] being separated from one another by an even distance which is sufficiently small to cause joinings during the assembly of the two silicon wafers. Said step [PLTS] of depositing the soldering bumps [PLTE] is carried out during the step of depositing the soldering bumps [PLTE] intended for the electrical contacts. The method includes a reflux soldering step [RFX] for assembling the two silicon wafers by melting of the alloy soldering bumps.

Abstract: A method and apparatus for encoding and decoding a bit stream by the use of a code word that comprises ones and zeros. The encoder is achieved by altering the bit stream such that the altered bit stream comprises a different combination of ones and zeros. The altered bit stream and the original bit stream are then encoded, transmitted, and decoded. The decoder accounts for the differing bit streams by reversing the effect of the altering.

Abstract: A system (15) comprising at least two integrated processors (P1 and P2). These two processors (P1 and P2) are operably connected via a communication channel (17) for exchanging information. One processor (P1) has a processor bus (10), a shareable unit (13), and a DMA unit (11) with an external DMA channel (12). The DMA unit (11) and the sharable unit (13) are connected to the processor bus (10). The other processor (P2) has an access unit (21) which is a connectable to the external DMA channel (12) of the DMA unit (11). Due to this arrangement, a communication channel (17) can be established from the access unit (21) which is connectable to the external DMA channel (12), the DMA unit (11), and the processor bus (10).

Abstract: The invention relates to a semiconductor device (10) comprising an electrically conductive bottom plate (1) on an upper side of which a semiconductor element (2) is positioned with a first connection region and a second connection region and with a first conductor and a second conductor, part of which is connected to, respectively, the first and the second connection region of the semiconductor element (2), the semiconductor element (2) and the parts of the conductors connected to the semiconductor element (2) being provided with an electrically insulating resin encapsulation (4) that covers a side face of the bottom plate (1), and the side face of the bottom plate (1) being provided, at the bottom face of the bottom plate (1), with a cavity (5) which is filled with a part of the encapsulation (4). According to the invention, the cavity (5), viewed in a direction transverse and perpendicular to the edge of the bottom plate (1), has the form of a staircase with to steps.

Abstract: The semiconductor device (11) of the invention comprises a circuit that is covered by a passivation structure. It is provided with a first security element (12) that comprises a local area of the passivation structure and which has a first impedance. Preferably, a plurality of security elements (12) is present, whose the impedances differ. The semiconductor device (11) further comprises measuring means (4) for measuring an actual value of the first impedance, and a memory (7) comprising a first memory element (7A) for storing the actual value as a first reference value in the first memory element (7A). The semiconductor device (11) of the invention can be initialized by a method wherein the actual value is stored as the first reference value. Its authenticity can be checked by comparison of the actual value again measured and the first reference value.

Abstract: An electronic circuit is provided that comprises a plurality of storage elements (101-105) arranged for storing of data elements, and a plurality of processing elements. The plurality of processing elements processes the data elements stored in the storage elements. In operation, the points in time at which respective storage elements load their data elements are mutually different in order to meet a maximum allowable value of the power consumption peaks.

Abstract: A membrane (20) has a membrane axis (5) and a middle area (50), a central cup-shaped depression (52) being provided around said membrane axis (5), which depression (52) preferably has a connecting channel (53), wherein the middle area (50) comprises groups of stiffening grooves (54, 55, 56, 57) which extend parallel to radial directions and of which a first group of long stiffening grooves (54, 55, 56) extends up to the depression (52), said connecting channel (53) issuing into two of the long stiffening grooves (55, 56), thus interconnecting these two long stiffening grooves (55, 56).

Abstract: A testing approach involves selective application of clock signals to target circuitry. In an example embodiment (300), a target circuit (332) having logic circuitry that processes data in response to an operational clock signal (308) having at least one clock period, is analyzed for delay faults. Test signals are applied to the logic circuitry while the logic circuitry is clocked with a high-speed test clock (309) having several clock-state transitions that occur during at least one clock period of the operational clock (308). An output from the logic circuitry is analyzed for its state (e.g., as affected by delay in the circuitry). Delay faults are detected as a difference in state of the output of the logic circuitry. With this approach, circuits are tested using conventional testers (340) that operate at normal (e.g., slow) speeds while selectively clocking selected portions of the circuit at higher speeds for detecting speed-related faults therein.

Abstract: A technique includes forming a first well in a substrate and forming a second well in the substrate. The first well is electrically isolated from the second well. The technique includes forming an element in the second well to limit current between the first well and the substrate.