Abstract: A communication apparatus includes a mechanism for preventing demodulation of text telephone information during reception of a poor quality signal. In one embodiment, the communication apparatus includes a receiver including a demodulator unit configured to receive a signal including a plurality of text telephone symbols. The demodulator unit may be configured to generate a soft decision based upon a frequency and an energy value of each received text telephone symbol. The demodulator unit may be configured to receive a notification that indicates the signal is unusable. In response to receiving the notification, the demodulator unit may be further configured to generate predetermined information that is independent of the plurality of text telephone symbols.

Abstract: A method for processing an input burst signal comprising a first step for identifying an additive DC component and generating an output signal, which is representative for an estimated value of said DC component. The method further comprises a second step for detecting a predetermined signal portion from a plurality of possible signal portions included in the input burst signal and generating a control signal indicating the presence of the predetermined signal portion in the input burst signal. The method is characterized in that the first step and the second step are performed in parallel i.e. in a commonly defined time interval from a starting time of the burst.

Abstract: The invention relates to a receiving circuit for receiving message signals, having a sampler for converting the message signal into a sampled signal, an analyzing unit for decoding the sampled signal and checking it for errors, and a control unit for controlling the sampling method as a function of the error-check on the sampled signal.

Abstract: The present invention relates to a data routing and processing device comprising a data bus, a router for managing communications on the data bus, data processing unit and a local memory for temporarily storing data. A transmitting processing unit transmits to the router an identifier. The router comprises a communication table which enables it to determine the receiving processing unit based on the identifier. The router ensures a communication between the transmitting processing unit and the receiving processing unit depending on a value of an availability register. If the receiving processing unit is available, the data transfer is direct; if not, the data transfer takes place via the local memory.

Abstract: A detection circuit for detecting the output power of a power amplifier comprises a first current minor transistor (Ti 1) having a base, which is connectable to a power transistor (T10), and a collector, a RF detection means (RF-det) for detecting the RF current flowing through the current mirror transistor (T11). Said RF detection means (RFdet) is connected to the collector of said first current mirror transistor (T11). Said detection circuit further comprises a biasing means (bias-RF-det) for biasing said RF detection means (RF-det), wherein said biasing means is connected to said collector of said first current mirror (T11) and said RF detection means (RF-det).

Abstract: A receiver apparatus including a main input for receiving the input signal and a first standard mixer having a first mixer input, a first local oscillator input, and a first mixer output. The first mixer input is connected to the main input and the first local oscillator input is connected to a source that provides a first local oscillator signal having a frequency close to or equal to the carrier frequency. The apparatus further including a second mixer with a second mixer input, a second local oscillator input, and a second mixer output. The second mixer input is connected to the main input and the second local oscillator input is connected to a source that provides a second local oscillator signal with an undesired sideband frequency. There are circuit for super-positioning the first output signal and the second output signal. The first local oscillator signal and the second local oscillator signal are square-wave signals.

Abstract: In a push-pull power amplifier having an end stage (10) in which two power transistors (ML, MH) are connected in series, a dead time is normally used to ensure that the power transistors do not conduct simultaneously. The invention provides an end stage in which the dead time can be omitted. This is achieved by dimensioning the driver circuits (11, 12) in such a way that during switching the control voltages (Vgh, Vgl) of the power transistors cross their threshold level (VT) substantially simultaneously.

Abstract: A method, apparatus, and system for converting an input voltage VIN to a digital output. A comparison of VIN with reference voltages in one or more flash-type analog-to-digital (A/D) converters generates the digital output representing VIN. If one A/D converter is used, the A/D converter is non-linear. If more than one A/D converter are used, the A/D converters are each linear.

Abstract: Voltage controlled oscillator comprising a LC tank circuit (L, C, R) coupled to modulator means and characterized in that the modulator means are coupled to amplifier means via an adder for generating a quadrature periodical output signal having a frequency in a relative wide range, the frequency being controlled by a control signal (V.sub.T) provided to the modulator means.

Abstract: In a data carrier (1) and in an integrated circuit (5), a first signal processing circuit (8) with a signal-independent power supply is provided for processing a signal stream (SF1) in accordance with a first transmission protocol, and a second signal processing circuit (9) with a signal-dependent power supply is provided for processing a signal stream (SF2) in accordance with a second transmission protocol, which signal stream (SF2) in accordance with the second transmission protocol comprises a signal characteristic, namely a lead signal (VLS), and a detection circuit (25) is provided, which detection circuit is designed for detecting the lead signal (VLS) and ensuring the supplying of the second signal processing circuit (9) with power from a power source (14) provided for the second signal processing circuit (9) following a recognition of the occurrence of the lead signal (VLS).

Abstract: A sliding bias circuit for dynamically controlling quiescent current flowing through an output transistor of a linear power amplifier operating in an output frequency band, the linear power amplifier comprising a circuit device for generating a bias signal producing a quiescent current flowing through the output transistor of the RF power amplifier, the sliding bias circuit comprising a detector circuit for detecting RF input to the amplifier and generating an output signal tracking the detected RF input, the output signal directly coupled to the circuit device for automatically modifying the bias signal and the quiescent current through the output transistor. In this manner, the quiescent current at the output stage is reduced and optimized for minimum dissipation and optimal linearity at all power output levels.

Abstract: The invention relates to a network comprising a plurality of network nodes. At least part of the network nodes are directly coupled to each other via at least one star node. The star node comprises a plurality of star interfaces which are assigned to at least one network node. In dependence on a respective pilot signal, a star interface conveys a message from the assigned network node to the other star interfaces, or from another star interface to at least one of the assigned network nodes. Also in the event of simultaneous arrival of at least two pilot signals at the respective star interfaces, a decision circuit releases one star interface for the transmission of data.

Abstract: Techniques are described for dynamically controlling the execution of operations within a multi-operation instruction, such as a very long instruction word (VLIW). A programmable processor fetches and executes a first instruction having an operation mask. Based on the operation mask, the processor selectively executes one or more operations within a second instruction. Individual operations within a multi-operation instruction can be selectively enabled and disabled, which is advantageous in many situations, including event handling and code debugging.

Abstract: An electronic signal processing apparatus has a signal switch with a first and a second transistor of normally-on type, having main current channels coupled between an internal node and a switch input and output, respectively. A diode provides a switchable signal coupling between the internal node and ground. A switch control circuit has a control output that is DC coupled to the main current channel of the first and the second transistor via the internal node to control conduction of the main current channels. The diode is also DC-coupled to the internal node so that a DC potential of a terminal of the diode that controls whether the diode is on or off is determined by a potential of the internal node. The diode is preferably incorporated in the DC current path from the control output to the internal node, so that the diode is forward-biased when a control voltage that makes the main current channels non-conductive is applied.

Abstract: A method and a circuit for producing a fail-safe output signal in case of an open circuit condition of an input pad of a digital circuit unit, comprising a first inverter stage providing a constant switch level; a second inverter stage providing a variable switch level that depends of the signal level of the input pad and comparing the constant switch level of the first inverter stage with the variable switch level of the second stage and providing an output signal at an output terminal thereof if the variable switch level of the second stage is greater than the constant switch level; and an additional circuit clement connected in series with the second inverter for decreasing the switch level of the second inverter stage.

Abstract: Apparatus (1) for continuous-time application, comprising an operational amplifier (2) and a self-zeroing control unit (3) for reducing an offset of the operational amplifier (2). The self-zeroing control unit (3) provides for a self zeroing operation mode and a normal operation mode. It comprises a comparator (6), a successive approximation register (7), and a digital-to-analog converter (8).

Abstract: A radio frequency (RF) linear power amplifier having an output transistor, and including a circuit means for generating a bias signal producing a quiescent current flowing through the output transistor, a detector circuit for detecting RF input to the amplifier and generating a driving signal according to a power level of the RF input; and a self-adaptable circuit for receiving the driving signal and automatically modifying the bias signal and the quiescent current through the output transistor. The quiescent current at the output stage is reduced and optimized for minimum dissipation and optimal linearity at all power output levels. The bias circuit for the radio frequency (RF) linear power amplifier includes a self-adaptable circuit that dynamically modifies the quiescent current for an output stage amplifier by automatically tracking an RF signal input to the amplifier at power ranges above a certain power output threshold.

Abstract: A diversity receiver (60) has two diverse channels fed by the antennas, an adaptive equalizer (20,30) for each channel and a coefficient adapter (40) for adapting two sets of coefficients in a time shared manner for the equalizers. A combiner combines the equalized signals. By sharing one adapter for adapting the coefficients between two or more equalizers, the calculation load can be reduced. This is useful for small mobile terminals powered by battery, for use with GSM or UMTS or other radio networks. It can be applied to any type of equalizer, and using any manner of time sharing. The combiner can exploit any type of diversity between the equalized signals. The equalizers can output two equalized signal values in consecutive time slots, by reusing the same coefficients, while new coefficients are being calculated.

Abstract: A semiconductor integrated circuit includes an inductor formed by a conductive loop that is fabricated on one or more metal layers. The inductor also includes a dielectric region provided adjacent to the conductive loop. The semiconductor integrated circuit may also include a pattern of electrically isolated metallic fill structures formed within the dielectric region.

Abstract: The invention relates to a tuner for converting a radio frequency signal into an intermediate frequency signal, said tuner comprising a voltage converter supplying a control signal, a mixer associated with an oscillator which is voltage-controlled by said control signal. The invention is characterized in that said voltage converter comprises: an auto-oscillating circuit generating an alternating voltage signal of a variable level, rectifying means for supplying a direct voltage signal of a variable level based on said alternating voltage signal of a variable level, an additional circuit for reducing the variations of the attenuation coefficient of said auto-oscillating circuit, said additional circuit receiving said direct voltage signal of a variable level and supplying said control signal. The invention provides an inexpensive solution having an improved performance in terms of spectral purity, ease of implementation and stability of control of said intermediate frequency signal.