Abstract: A fault collection and reaction system on a system-on-chip (SoC) includes a plurality of reaction cores assigned to a plurality of applications being executed by a plurality of processor cores on the SoC, at least one look-up table (LUT), and a controller. The at least one LUT stores therein a first mapping between the plurality of reaction cores and corresponding plurality of domain identifiers, and a second mapping between a plurality of faults and a set of reaction combinations. The controller receives a fault indication and a first domain identifier in response to occurrence of a first fault and selects from the plurality of reaction cores, a first reaction core mapped to the first domain identifier, and from the set of reaction combinations, a first reaction combination mapped to the first fault. The first reaction core responds to the fault indication with a reaction based on the selected reaction combination.

Abstract: Interconnected substrate arrays, microelectronic packages, and methods for fabricating microelectronic packages for fabricating microelectronic packages utilizing interconnected substrate arrays containing integrated electrostatic discharge (ESD) protection grids are provided. In an embodiment, the method includes obtaining an interconnected substrate array having an integrated ESD protection grid. The ESD protection grid includes, in turn, ESD grid lines at least partially formed in singulation streets of an interconnected substrate array and electrically coupling die attachment regions of the substrate array to one or more peripheral machine ground contacts. Array-level fabrication steps are performed to produce an interconnected package array utilizing the interconnected substrate array, while electrically coupling the die attachment regions to electrical ground through the ESD protection grid during at least one of the array-level fabrication steps.

Abstract: A semiconductor device includes a substrate having opposed first and second major surface, an active area, and a termination area. Insulated trenches extend from the first major surface toward the second major surface, each of the insulated trenches including a conductive field plate and a gate electrode overlying the conductive field plate, the gate electrode being separated from the field plate by a gate-field plate insulator. The field plate extends longitudinally in both of the active and termination areas and the gate electrode is absent in the termination area. A body region of a first conductivity type extends laterally between pairs of the insulated trenches. First and second spacer regions of a second conductivity type extend laterally between the pairs of the insulated trenches at the termination area to produce segments of the first conductivity type between the first and second spacer regions that are isolated from the body region.

Abstract: A secure read-only-memory (ROM) code patching system includes a processor that is configured to generate first partial cryptographic data based on a ROM patch and a set of secret bits, and authenticate the ROM patch based on a match between the first partial cryptographic data and reference partial cryptographic data of the ROM patch. Upon the authentication of the ROM patch, the processor is further configured to generate an address associated with a set of ROM instructions of a ROM code. Based on a match between the generated address and a ROM patch address of the ROM patch, the processor is further configured to execute a set of patch instructions of the ROM patch that is successfully authenticated instead of the set of ROM instructions, thereby securely patching the ROM code.

Abstract: A memory management system for facilitating communication between an interconnect and a system memory of a system-on-chip includes a plurality of memory controllers coupled with the system memory, and processing circuitry coupled with the interconnect and the plurality of memory controllers. The processing circuitry is configured to receive a transaction request from the interconnect, and identify a memory controller of the plurality of memory controllers that is associated with the received transaction request. Further, the processing circuitry is configured to provide the transaction request to the identified memory controller for an execution of a transaction associated with the received transaction request.

Abstract: A method for controlling access to a chip includes obtaining first values of a first physically unclonable function of the chip, obtaining second values that correspond to at least one challenge word, performing a simulation based on the first values and the second values, and generating an authentication result for the chip based on results of the simulation. The simulation may generate responses to logical operations corresponding to combinatorial logic in the chip, and the logical operations may be performed based on a predetermined sequence of the first values and the second values. The chip may be authenticated based on a match between the responses generated by the simulation and a second physically unclonable function of the chip.

Abstract: In accordance with a first aspect of the present disclosure, a near field communication (NFC) device is provided, comprising: an NFC front-end circuit configured to perform a communication with an external device; at least one processing unit configured to process one or more transactions between the NFC device and the external device; an NFC controller configured to control the NFC front-end circuit; wherein the NFC controller is configured to block a current data frame, which is being received by the NFC front-end circuit, if the processing unit has not fully processed a previous data frame. In accordance with a second aspect of the present disclosure, a corresponding method of operating a near field communication (NFC) device is conceived. In accordance with a third aspect of the present disclosure, a corresponding computer program is provided.

Abstract: Communication apparatus includes a transceiver configured to transmit and receive signals over a wireless channel in accordance with both a first communication protocol and a second communication protocol, the second communication protocol being backward-compatible with the first communication protocol. The transceiver is configured to provide capabilities that are supported by the second communication protocol but are not supported by the first communication protocol. A communication controller is configured to generate data frames for transmission by the transceiver. The date frames include frame headers that are compatible with the first communication protocol while including, in a specified field of the frame headers, a predefined value indicating that the apparatus is capable of communicating in accordance with the second communication protocol.

Abstract: A method of scaling complexity of a video processing system including determining a power saving factor based on an operating parameter and adjusting processing of video information based on the power saving factor to reduce computation complexity. The operating parameter may include available power and/or available processing capacity. A method of complexity scalability for a video processing system using prioritized layered coding including determining a power saving factor based on one or more metrics, such as power capacity and/or available processing capacity, and reducing processing complexity of multiple prioritized coding functions in a predetermined order of priority based on the level of the power saving factor. A video processing system including a power management circuit which determines the power saving factor and a video encoder system which correspondingly adjusts computation complexity.

Abstract: A data processing system and a method are provided for recognizing a scanned biometric characteristic in the data processing system. The data processing system includes a biometric sensor, a rich execution environment (REE), and a secure element (SE). In one embodiment, during an enrollment operation, a random challenge is applied to scanned data to produce a biometric template that is stored. During subsequent validation operations, the SE determines if user data includes evidence of the random challenge before providing access to a secure application. Evidence of the random challenge indicates the user data was provided by the biometric sensor. In another embodiment, the sensor data is split between the REE and the SE and partially processed in the SE. The described embodiments prevent a replay attack from being conducted in communications between the REE and the SE.

Abstract: A transistor device having a channel region including a portion located in a sidewall of semiconductor material of a trench and an extended drain region including a portion located in a lower portion of the semiconductor material of the trench. In one embodiment, a control terminal of the transistor device is formed by patterning a layer of control terminal material to form a sidewall in the trench and a field plate for the transistor device is formed by forming a conductive sidewall spacer structure along the sidewall of the control terminal material.

Abstract: A base station includes a millimeter wave communication unit coupled to an impulse radio ultra-wideband (IR-UWB) communication unit. The millimeter wave communication unit is capable of being wirelessly coupled to user-equipment using a millimeter wave communication link. Based on a determination as to whether the user-equipment is configured for IR-UWB ranging and localization, an IR-UWB communication link is established between the base station and user-equipment for IR-UWB ranging and localization. When the IR-UWB communication link is established for IR-UWB ranging and localization, the ranging and localization associated with the millimeter wave communication unit is disabled and the millimeter wave communication link is used for data communication maximizing throughput by utilizing localization and ranging information provided by the IR-UWB communication link.

Abstract: A memory includes memory cells having two select transistors per cell. Each of the two select transistors are coupled to two different word lines with each word line being controlled by a separate addressable word line driver circuit. In some embodiments, providing two different word lines from two different word line drivers may provide for a memory where the word lines can apply different voltages based on the memory operation being performed.

Abstract: A communication unit (300) is described that includes a plurality of cascaded devices that includes at least one master device and at least one slave device configured in a master-slave arrangement. The at least one master device comprises a modulator circuit (362) configured to: receive a system clock signal and a frame start signal; modulate the system clock signal with the frame start signal to produce a modulated master-slave clock signal (384); and transmit the modulated master-slave clock signal (384) to the at least one slave device. The at least one slave device comprises a demodulator circuit (364) configured to: receive and demodulate the modulated master-slave clock signal (384); and re-create therefrom the system clock signal (388, 385) and the frame start signal (390, 386).

Abstract: An ultra-wideband (UWB) wireless communication system, comprises a first wireless apparatus; a second wireless apparatus that participates in a first ranging sequence with the first wireless apparatus; and a transmission channel between the first and second wireless apparatuses that transmits data of the first ranging sequence. At least one of the first wireless apparatus or second wireless apparatus generating at least one channel impulse response (CIR) and determining from the at least one CIR whether the transmission channel includes a line-of-sight channel. A special purpose processor reduces a current performance level of at least one of the first and second wireless apparatuses during a second ranging sequence in response to a determination that the transmission channel includes the line-of-sight channel.

Abstract: Dynamic address allocation of multiple device instances of an improved inter-integrated circuit (I3C) target device by an I3C controller device is disclosed. A first device instance is configured to receive a command and a clock signal from the I3C controller device, and further receive a first status signal that is indicative of a first device instance ID of the first device instance. The first device instance is further configured to decode the command based on the first status signal and the clock signal, and generate a response that includes the first device instance ID. The I3C controller device is configured to allocate a dynamic address to the first device instance based on the response. The first device instance is then configured to generate and provide a second status signal to a second device instance for facilitating dynamic address allocation of the second device instance.

Abstract: A method for protecting a machine learning (ML) model is provided. During inference operation of the ML model, a plurality of input samples is provided to the ML model. A distribution of a plurality of output predictions from a predetermined node in the ML model is measured. If the distribution of the plurality of output predictions indicates correct output category prediction with low confidence, then the machine learning model is slowed to reduce a prediction rate of subsequent output predictions. If the distribution of the plurality of categories indicates correct output category prediction with a high confidence, then the machine learning model is not slowed to reduce the prediction rate of subsequent output predictions of the machine learning model. A moving average of the distribution may be used to determine the speed reduction. This makes a cloning attack on the ML model take longer with minimal impact to a legitimate user.

Abstract: A power source switching circuit is disclosed. The power source switching circuit includes a voltage regulator, a first transistor and a second transistor. The first transistor is coupled with a first voltage source and the second transistor is coupled with a second voltage source. The voltage regulator includes a resistor, one or more diodes coupled together in series and a capacitor. Terminals of the capacitor are coupled between a gate and a source of the first transistor through a first switch and a second switch respectively. The capacitor is configured to hold charge to switch the first transistor on. A value of the capacitor is smaller than a gate to source capacitance of the first transistor.

Abstract: Embodiments of a circuit, system, and method are disclosed. In an embodiment, a circuit includes a first microstrip transmission line, a second microstrip transmission line, and a slotline formation, wherein the slotline formation extends between the first microstrip transmission line and the second microstrip transmission line so that the slotline formation is configured to electromagnetically couple the first microstrip transmission line to the second microstrip transmission line during operation of the circuit. In addition, the circuit includes at least one controllable capacitance circuit electrically connected to at least one of the first microstrip transmission line and the second microstrip transmission line, wherein a magnitude of capacitance of the at least one controllable capacitance circuit is controllable (e.g., in response to a capacitance control signal received at a control interface).

Abstract: An embodiment of a heating system includes a cavity configured to contain a load, a thermal heating system, and an RF heating system. The RF heating system includes a system controller, an RF signal source, one or more electrodes that receive an RF signal from the RF signal source and radiate resultant electromagnetic energy into the cavity, and a variable impedance matching network coupled between the RF signal source and the one or more electrodes. The system controller may monitor an impedance state of the variable impedance matching network to identify the occurrence of a change point. The system controller may estimate the mass of the load and a time and/or energy requirement for cooking the load based on the change point. The system controller may take action by turning off the RF heating system and/or thermal heating system when the time or energy requirement has been met.