Abstract: An integrated circuit includes a first processing domain configured to run a first operating system and a second processing domain configured to run a second operating system that is different than the first operating system. The integrated circuit further includes a time stamp timer circuit in the first processing domain configured to provide a first time stamp value to the first processing domain and an adjusted second time stamp value to the second processing domain. The time stamp timer circuit includes a timer adjust circuit configured to synchronize the adjusted second time stamp value when a power up signal is received by the time stamp timer circuit from the second processing domain.

Abstract: One example discloses a device including a near-field electromagnetic induction (NFEMI) antenna, including: a first inductive coil having a first end coupled to a first feed connection and a second end coupled to a second feed connection; a second inductive coil, having a first end coupled to either end of the first inductive coil or either one of the feed connections; wherein a second end of the second inductive coil is electrically open-ended; wherein the first inductive coil is configured to receive or transmit near-field magnetic signals; and wherein the second inductive coil is configured to receive or transmit near-field electric signals.

Abstract: A first switch is operable to couple a start-up oscillator circuit to a first crystal pin during operation in a start-up mode and decouple the start-up oscillator circuit from the first crystal pin during operation in a normal mode, and a second switch is operable to couple the start-up oscillator circuit to a second crystal pin during operation in the start-up mode and decouple the start-up oscillator circuit from the second crystal pin during operation in the normal mode. A switched oscillator circuit is coupled to the startup oscillator during operation in the startup mode, and to the first and second crystal pins during operation in the start-up and normal modes. The switched oscillator circuit includes a sample and charge circuit which is configured to sample a direct current (DC) level of the first crystal pin and pre-charge a first coupling capacitor during operation in the startup mode.

Abstract: The disclosure relates to a transceiver and associated method and computer program. The transceiver comprises a transmitter for transmitting, based on an input signal, a transmitter output voltage to a differential signaling bus, the transceiver configured to: generate, from the input signal, a copy of the transmitter output voltage to provide an expected differential bus voltage; measure a differential bus voltage from the differential signaling bus; and detect an error frame on the differential signaling bus based on a comparison between the measured differential bus voltage and the expected differential bus voltage.

Abstract: A processor scheduling structure, a method and an integrated circuit are provided. In accordance with at least one embodiment, the processor scheduling structure comprises a processor circuit and an operating system task aware caching (OTC) controller circuit coupled to the processor circuit. The OTC controller circuit comprises a load request timer, a load sequence queue (LSQ), and a request arbiter. The timer and the LSQ are coupled to and provide inputs to the request arbiter. The processor circuit comprises an internal memory and a processor core. The OTC controller circuit is configured to schedule processor tasks for the processor circuit in accordance with both priority-based scheduling, using the LSQ, and time-triggered scheduling, using the load request timer.

Abstract: One example discloses a differential-signal-detection circuit, including: an input stage configured to receive a differential input signal and to output a first differential output signal and a second differential output signal; a first comparator coupled to receive both the first differential output signal and the second differential output signal, and in response generate a first comparator output signal; a second comparator coupled to receive both the first differential output signal and the second differential output signal and generate a second comparator output signal; and an output stage configured to receive the first and second comparator output signals and generate a differential-signal-detection signal; wherein the output stage includes a deglitch circuit configured to attenuate changes in the differential-signal-detection signal during an inter-symbol period of the differential input signal.

Abstract: One example discloses a power management circuit, including: an ultrasonic transmitter configured to generate an ultrasonic signal having a set of transmitted ultrasonic signal attributes; an ultrasonic receiver configured to detect the ultrasonic signal having a set of received ultrasonic signal attributes; wherein the power management circuit is configured to cause a device to be operated at a first power level and a second power level; and a proximity detection circuit configured to transition the device from the first power level to the second power level in response to a preselected difference between the transmitted set of ultrasonic signal attributes and the received set of ultrasonic signal attributes.

Abstract: Embodiments of a device and method are disclosed. In an embodiment, a method of communications involves at a communications device, detecting an erroneously transmitted packet based on a communications protocol associated with the erroneously transmitted packet, and from the communication device, notifying a wired communications network of the erroneously transmitted packet.

Abstract: A local control-unit operable as a master or a slave comprises: a memory indicative of whether the converter sub-unit is enabled or disabled; and an enable; a wake-up output; a communication link input and output interfaces configured to receive and to send master/slave information; and a further communication link input and output interfaces, configured to both enable current balancing and phase interleaving with other enabled converter sub-units; and being adapted and configured to: in response to the respective local output current being higher than a first threshold, send a wake-up request to the next converter sub-unit; and in response to (a) being a slave sub-unit; (b) the respective local output current being lower than a second threshold, and (c) receiving master/slave information indicative that the next enabled sub-unit is a master sub-unit, disabling itself. Methods of operating the same are also disclosed.

Abstract: Area and routing overhead issues of traditional anamux incorporation in a semiconductor device are overcome by placing a functional anamux block on top of an I/O pad. In some embodiments, multiple anamux blocks can be stacked either vertically or placed on neighboring I/O pads for horizontal stacking. Embodiments provide the anamux blocks as the same width as the I/O pads and the width is optimized to minimize padring height. In some embodiments, a power/ground I/O (PGE) bond pad architecture is enabled by the incorporation of both I/O pad and anamux blocks in the same region, providing two bonding regions, which can further reduce chip area. Some embodiments also permit routing of signals through the anamux block to neighoring blocks and the I/O channels.

Abstract: A fully digital method and apparatus are provided for detecting glitches on a monitored line by providing a toggle signal to an initial delay circuit and a plurality of delay elements formed with standard logic cells so that logic values from the delay elements are captured in a corresponding plurality of clocked capture flops to provide a digitized representation of a delay value during a sampling period which is converted to a numerical measurement result which is evaluated against a reference value to generate an output error signal if a difference between the numerical measurement result and reference value exceeds a programmable margin, where the initial delay circuit is configured with a trim setting to impose an initial delay to compensate for process variations and where the reference value is adapted over a plurality of sampling periods to compensate for temperature effects on the numerical measurement result.

Abstract: A radar device (100) is described that includes at least one transceiver (105) configured to support frequency modulated continuous wave (FMCW); radar device (100) and a digital controller (262). A temperature sensor system includes a plurality of temperature sensors (222, 232, 242) coupled to one or more circuits (220, 230, 240) in the at least one transceiver (105). The digital controller (262, 306) comprises or is operably coupled to an over-temperature emulation circuit (308) configured to emulate an over-temperature shutdown state by injecting an over-temperature force signal (290) into the temperature sensor system (270).

Abstract: A memory controller for a (DRAM) memory processes an (access) command for a target row in the memory, increments a count value for each victim row associated with the target row, and issues a (dummy activate) command for a victim row whose count value reaches a specified threshold. By tracking victim rows instead of target rows, the memory controller can thwart both single-sided and double-sided row-hammer attacks. The memory controller maintains the victim-row addresses and corresponding command counts in a TCAM memory to detect rows that may be prone to row-hammer attacks. If so, then the memory controller issues dummy activate commands to the corresponding memory rows to thwart such row-hammer attacks.

Abstract: A centralized access control circuit includes a memory, a sub-circuit, and a memory controller. The memory includes a plurality of lock bits mapped to a plurality of bytes of a peripheral register included in a peripheral. The sub-circuit receives, from a processor core, an access request to access a set of bytes of the plurality of bytes. The sub-circuit grants a first level of access privilege to the processor core based on an identifier of the processor core and an address of the set of bytes included in the access request. The memory controller receives the access request and grants, based on a value of each of a set of lock bits mapped to the set of bytes, a second level of access privilege to the processor core. The processor core accesses the set of bytes based on the first and second levels of access privileges.

Abstract: A millimeter-wave wireless multiple antenna system (80) and method (100) are provided in which a UE (120) uses a multi-antenna subsystem (81) to identify a plurality of m strongest transmit beams (122) from the base station (110) based on power measurements of a plurality of synchronization signal blocks (SSBs) transmitted on a corresponding plurality of transmit beams by the base station (110), and to generate multiple uplink random access channel (RACH) preambles (123) that is sent (124) to the base station (110) to identify the plurality of m strongest transmit beams and relative weights for each of the plurality of m strongest transmit beams which are used by the base station (112) to generate an optimal downlink transmit beam for use in sending a RACH response to the UE (120).

Abstract: A data processing device and method for detecting interference in a FMCW radar system are described. For each of a plurality of transmitted chirps of the radar system, a high pass filter is applied to a receiver signal of a receiver channel of a radar receiver during an acquisition time corresponding to a transmitted chirp to remove those parts of the receiver signal corresponding to a reflected chirp having a power at the radar receiver greater than the noise power of the radar receiver of the radar system. The receiver signal power is calculated from the high pass filtered receiver signal. The receiver signal power is compared with a threshold noise power based on an estimate of the thermal noise of the radar receiver to determine whether the receiver signal corresponds to an interfered received chirp including interference or a non-interfered received chirp not including interference.

Abstract: A self-calibrating digital-to-analog converter (DAC) is disclosed. The self-calibrating DAC includes an input port, a non-binary DAC, an ADC to receive an output of the non-binary DAC, a lookup table to store a plurality of calibration code and a calibration logic coupled with the non-binary DAC. The self-calibrating DAC has two modes of operations, a calibration mode and a normal operational mode. In the calibration mode, the self-calibrating DAC is configured to calculate weightages of the non-binary DAC and to calculate an offset coefficient and a gain coefficients using high precision on chip analog-to-digital converter (ADC).

Abstract: A bandgap voltage regulator includes a proportional-to-absolute-temperature (PTAT) circuit, an amplifier, and a driver circuit. The PTAT circuit can include various transistors that output a corresponding control voltage. The amplifier generates another control voltage to compensate base-current variations associated with the transistors of the PTAT circuit. The control voltage is generated by the amplifier based on the control voltage outputted by the PTAT circuit, and one of a base-emitter voltage associated with a transistor of the PTAT circuit, a scaled down version of the control voltage outputted by the amplifier, and a scaled down version of the base-emitter voltage. The driver circuit outputs, based on a supply voltage and the control voltages outputted by the PTAT circuit, a reference voltage for driving a functional circuit.

Abstract: Examples of wireless communication based on link use capabilities of multi-link devices is disclosed. A first multi-link device receives a first physical layer conformance procedure (PLCP) protocol data unit (PPDU) on a first link from a second multi-link device and transmits a second PPDU on the second link based on a link use capability of the second multi-link device and a backoff counter counting down to a predetermined value. A first multi-link device also transmits a PPDU on the first link and the second link at a same start time based on an link idle determination and the backoff counter counting down to a predetermined value.

Abstract: A method that incorporates teachings of the subject disclosure may comprise, for example, selecting a barium-strontium-titanate (BST) material, wherein the BST material has a perovskite lattice structure with at least a first lattice constant and a second lattice constant; selecting a strontium-barium-niobate (SBN) material, wherein the SBN material has a lattice structure with at least a third lattice constant and a fourth lattice constant, wherein the third lattice constant is substantially equal to the first lattice constant, and wherein the fourth lattice constant is substantially equal to the second lattice constant; and growing, on a grain boundary region of the BST material, the SBN material, wherein the growing is via self-assembly, and wherein the growing is facilitated by the third lattice constant of the SBN material being substantially equal to the first lattice constant and the fourth lattice constant of the SBN material being substantially equal to the second lattice constant.