Abstract: A co-prime coded DDM MIMO radar system, apparatus, architecture, and method are provided with a reference signal generator (112) that produces a transmit reference signal; a plurality of DDM transmit modules (11) that produce, condition, and transmit a plurality of transmit signals over which each have a different co-prime encoded progressive phase offset from the transmit reference signal; a receiver module (12) that receives a target return signal reflected from the plurality of transmit signals by a target and generates a digital signal from the target return signal; and a radar control processing unit (20) configured to detect Doppler spectrum peaks in the digital signal, where the radar control processing unit comprises a Doppler disambiguation module (25) that is configured with a CPC decoder to associate each detected Doppler spectrum peak with a corresponding DDM transmit module, thereby generating a plurality of transmitter-associated Doppler spectrum peak detections.

Abstract: A wideband buffer circuit and a wideband communication circuit that uses the wideband buffer circuit. The wideband buffer circuit includes first and second transistors deployed as a voltage buffer and connected to first and second input terminals, first and second parallel resistor-capacitor pairs connected to the first and second transistors, first and second cross-coupled transistors connected to the first and second parallel resistor-capacitor pairs and connected to first and second output terminals, and first and second current sources connected to the first and second cross-coupled transistors and a fixed voltage. The first transistor, the first parallel resistor-capacitor pair, the first cross-coupled transistor and the first current source are connected in series. The second transistor, the second parallel resistor-capacitor pair, the second cross-coupled transistor and the second current source are connected in series.

Abstract: Example systems have a defrost system that can receive a first RF signal at a first frequency to defrost a load. An air treatment device can receive a second RF signal at a second frequency and perform an air treatment process. An RF signal source has a power output, and a switching arrangement selectively electrically connects the defrost system and the first air treatment device to the power output of the RF signal source. A controller can electrically connect one of the defrost system and the first air treatment device to the power output of the RF signal source. When the defrost system is electrically connected, the RF signal source outputs the first RF signal at the first frequency, and when the first air treatment device is electrically connected, the RF signal source outputs the second RF signal at the second frequency.

Abstract: Power amplifier (PA) packages, such as Doherty PA packages, containing multi-path integrated passive devices (IPDs) are disclosed. In embodiments, the PA package includes a package body through which first and second signal amplification paths extend, a first amplifier die within the package body and positioned in the first signal amplification path, and a second amplifier die within the package body and positioned in the second signal amplification path. A multi-path IPD is further contained in the package body. The multi-path IPD includes a first IPD region through which the first signal amplification path extends, a second IPD region through which the second signal amplification path extends, and an isolation region formed in the IPD substrate a location intermediate the first IPD region and the second IPD region.

Abstract: Embodiments of a device and method are disclosed. In an embodiment, a method of communications involves generating a packet for communications in a wired communications network, where the packet includes a header and a payload, and where the header includes packet type information that indicates a network connection within the wired communications network in which the packet is used, and transmitting the packet through the network connection.

Abstract: A memory includes virtual ground circuitry configured to generate a virtual ground voltage (greater than zero volts) at a virtual ground node, a memory array of resistive memory cells in which each resistive memory cell includes a select transistor and a resistive storage element and is coupled to a first column line of a plurality of first column lines, and a first decoder configured to select a set of first column lines for a memory read operation from a selected set of the resistive memory cells. The memory includes read circuitry, and a first column line multiplexer configured to couple each selected first column line of the set of first column lines to the read circuitry during the memory read operation, and configured to couple each unselected first column line of the plurality of first column lines to the virtual ground node during the memory read operation.

Abstract: A camera interface circuit for a barcode scanner includes a binary conversion block and a selection module. The binary conversion block receives image signals from a camera, and converts gray levels of each pixel in each image frame into binary codes. The selection module alternately provides binary codes of one image frame and image signals of a consecutive image frame as outputs.

Abstract: A power splitter for use in an amplifier (e.g., a Doherty amplifier) includes an input terminal, and first and second output terminals. The input terminal is configured to receive an input RF signal, the first output terminal is configured to produce a first RF output signal, and the second output terminal is configured to produce a second RF output signal. The power splitter also includes a first capacitance electrically coupled between the input terminal and the first output terminal, a second capacitance electrically coupled between the input terminal and the second output terminal, a first inductance electrically coupled between the input terminal and a ground reference node, a second inductance electrically coupled between the first output terminal and the ground reference node, a third inductance electrically coupled between the second output terminal and the ground reference node, and a resistance electrically coupled between the first and second output terminals.

Abstract: A method for Wireless Local-Area Network (WLAN) communication in a WLAN device includes receiving from a remote WLAN device an announcement of a maximal Hybrid Automatic Repeat Request (HARQ) buffering capability of a receiver of the remote WLAN device. A HARQ Physical-layer Protocol Data Unit (HARQ PPDU), which includes one or more HARQ coding units, is constructed in the WLAN device in response to the announcement. The HARQ PPDU is transmitted from the WLAN device to the remote WLAN device. One or more of the HARQ coding units are retransmitted in response to a request from the remote WLAN device.

Abstract: A switch comprising: a channel path comprising first and second MOS transistors with common source and gate terminals and drain terminals defining first and second terminals of the channel path; and control circuitry comprising: a third MOS transistor comprising: a gate coupled to the common source terminal; a source coupled to the common gate terminal by a resistor; and a drain coupled to a first reference terminal; a first current source coupled between the first reference terminal and the common gate terminal for providing a first current; a second current source coupled between the source terminal of the third MOS transistor and a second reference terminal for providing a second current greater than the first current; and a first switching arrangement configured to selectively enable and disable the first current source; and a second switching arrangement configured to selectively couple the common source terminal to the second reference terminal.

Abstract: Leadless power amplifier (PA) packages and methods for fabricating leadless PA packages having topside terminations are disclosed. In embodiments, the method includes providing electrically-conductive pillar supports and a base flange. At least a first radio frequency (RF) power die is attached to a die mount surface of the base flange and electrically interconnected with the pillar supports. Pillar contacts are further provided, with the pillar contacts electrically coupled to the pillar supports and projecting therefrom in a package height direction. The first RF power die is enclosed in a package body, which at least partially defines a package topside surface opposite a lower surface of the base flange. Topside input/out terminals are formed, which are accessible from the package topside surface and which are electrically interconnected with the first RF power die through the pillar contacts and the pillar supports.

Abstract: An embodiment of an electronic device includes a circuit component (e.g., a transistor or other component) coupled to the top surface of a substrate. Encapsulation is formed over the substrate and the component. An opening in the encapsulation extends from the encapsulation top surface to a conductive feature on the top surface of the component. A conductive termination structure within the encapsulation opening extends from the conductive feature to the encapsulation top surface. The device also may include a second circuit physically coupled to the encapsulation top surface and electrically coupled to the component through the conductive termination structure. In an alternate embodiment, the conductive termination structure may be located in a trench in the encapsulation that extends between two circuits that are embedded within the encapsulation, where the conductive termination structure is configured to reduce electromagnetic coupling between the two circuits during device operation.

Abstract: It is described a leakage compensation circuit for a measurement device which comprises a measurement circuit with a leaking device that is connected to a measurement path and causes a leakage current. The leakage compensation circuit comprises: i) a replica device of the leaking device, wherein the replica device is connected to a replica path, and wherein the replica device is configured to cause a replica leakage current that is essentially equal to the leakage current of the leaking device, ii) a voltage regulator which is connected to the measurement path and to the replica path, wherein the voltage regulator is configured to regulate the voltage in the replica path based on the voltage of the measurement path, and iii) a current mirror which is connected to the measurement path and to the replica path, wherein the current mirror is configured to mirror the replica leakage current of the replica device into the measurement path.

Abstract: Aspects of the subject disclosure may include a Doherty amplifier that includes a carrier amplifier having an output terminal, an output network coupled to the output terminal, and a peaking amplifier, wherein the output network comprises a non-linear reactance component, and wherein the non-linear reactance component changes an effective impedance of a load presented to the carrier amplifier when the peaking amplifier is off. Other embodiments are disclosed.

Abstract: A wireless charger includes a rectifier, a first filter that includes an inductor, a resonant tank circuit, and a second filter that includes a switch. The rectifier receives a drive signal from a voltage supply and generates a rectified voltage signal. The rectified voltage signal is filtered by the first filter and the filtered signal is provided to the tank circuit, which resonates to provide power wirelessly to a receiver. The switch of the second filter is connected in parallel with the inductor of the first filter. The switch is closed in order to bypass the inductor during a detection phase in which the wireless charger determines a quality factor of the tank circuit.

Abstract: A power management integrated circuit comprises a modular interleaved clock generator comprising a plurality of interconnected modular elements, each element constructed to generate and output a clock signal, and each one comprising: a phase port high input; a phase port low input; a clock input; and a bypass switch coupled between the phase port high input and the phase port low input, wherein in response to the bypass switch of at least one of the plurality of elements in a closed state, the phase port high inputs or the phase port low inputs of the remaining elements absent the at least one interleaving controller having the bypass switch in the closed state each receives a voltage that interleaves the clock signals output from the remaining active elements to have an interleaving arrangement that includes equal phase delays.

Abstract: A frequency synthesizer is described that includes: a voltage controlled oscillator, VCO; a VCO bias circuit, operably coupled to the VCO and configured to provide a controllable bias current of the VCO; a temperature sensor, located in the frequency synthesizer, configured to determine an operating temperature of the frequency synthesizer; an analog-to-digital converter, ADC, operably coupled to the temperature sensor and configured to provide a digital representation of the determined operating temperature; and a bias control circuit operably coupled and configured to provide a bias control signal to the VCO bias circuit based on the determined operating temperature of the frequency synthesizer. The VCO bias circuit is configured to adjust the controllable bias current applied to the VCO based on the bias control signal.

Abstract: A semiconductor device package that incorporates a waveguide usable for high frequency applications, such as radar and millimeter wave is provided. Embodiments employ a rigid-flex printed circuit board structure that can be folded to form the waveguide while, at the same time, mounting one or more semiconductor device die or packages. Embodiments reduce both the area of the mounted package and the distance signals need to travel between the semiconductor device die and antennas associated with the waveguide.

Abstract: A current monitor includes current sense logic and a processor. The current sense logic senses inductor current at a predetermined time point during operation of a constant on-time regulator. The processor determines output current of the constant on-time regulator based on the inductor current sensed at the predetermined time point. The predetermined time point corresponds to half of an on-time period of the constant on-time regulator. The output current may be determined during continuous conduction mode (CCM) or discontinuous conduction mode (DCM). During DCM mode, the processor determines the output current of the constant on-time regulator based on a skip time.

Abstract: Embodiments of a method and device are disclosed. In an embodiment, a controller includes a plurality of memories each having registers that are accessible using an address, a plurality of memory controllers each coupled to a memory and configured to control read and write operations to the respective coupled memory, a bus coupled to each of the memory controllers configured to communicate data and commands to each of the memory controllers, a plurality of processing cores coupled to the bus and configured to read and write data to the memories through the memory controllers, and a plurality of isolation stages, each isolation stage being coupled between a memory controller and a memory and configured to isolate the respective memory from receiving a memory clock signal when the memory is not addressed by the memory controller.