Abstract: A thermal increase system includes one or more multi-level electrodes configured to radiate electromagnetic energy into a cavity in response to receiving a radio frequency (RF) signal from an RF signal source. Each multi-level electrode is positioned adjacent to a wall of the cavity, and each multi-level electrode includes a base portion coupled to an elevated portion. A radiating surface of the elevated portion is at a height of at least 0.5 centimeters (cm) from a radiating surface of the base portion.

Abstract: In accordance with a first aspect of the present disclosure, a user authentication system is provided, comprising: a user authentication token, said user authentication token comprising a fingerprint sensor and a secure element; an assistance device configured to be coupled to the user authentication token through an interface of said user authentication token; wherein the assistance device is configured to request the secure element to verify a personal unlock key to be captured by the secure element through the fingerprint sensor; wherein the secure element is configured to capture the personal unlock key through the fingerprint sensor, to verify the captured personal unlock key and to enroll, upon or after a positive verification of the personal unlock key, fingerprint reference data captured through the fingerprint sensor. In accordance with a second aspect of the present disclosure, a corresponding method for enrolling fingerprint reference data in a user authentication token is conceived.

Abstract: A Radio Frequency Identification (RFID) tag is disclosed. The RFID tag includes an antenna port to receive an input AC signal and a self-tuning circuit coupled with the antenna port to optimize signal strength of the input AC signal during a self-tuning phase. The RFID tag further includes an AC limiter configured to limit the voltage of the input AC signal to a preconfigured limit and a limiter controller configured to disable the AC limiter during the self-tuning phase and re-enable the AC limiter after the self-tuning phase. The self-tuning phase occurs prior to the data communication period in which the data stored in the RFID tag is transmitted back to a reader.

Abstract: In accordance with a first aspect of the present disclosure, a method is conceived for enabling a biometric template in an authentication token, the method comprising: capturing, by a biometric sensor comprised in the authentication token, at least one biometric sample; creating, by a processing unit comprised in the authentication token, a biometric template from the at least one biometric sample and storing said biometric template in the authentication token; verifying, at a terminal device, said biometric template; verifying, by the terminal device, an identity of a user; enabling, by the terminal device, said biometric template if the biometric template and the identity of the user have been verified. In addition, a corresponding computer program, authentication token and terminal device are provided.

Abstract: The disclosure relates to patch antennas for radar or communications applications. Example embodiments include an antenna comprising: a substrate; a ground plane on a first face of the substrate; and a patch antenna on an opposing second face of the substrate, the patch antenna having a lead extending along a central axis and connected to a rectangular radiating element, wherein the rectangular radiating element comprises two slots on opposing sides of the central axis such that the patch antenna has two resonant frequencies within an operating frequency range of the antenna.

Abstract: An interrupt rate limiter limits the rate of interrupt signals being transmitted from a first node to a second node of a computer system. In certain implementations, a first logic block compares an accumulator value to a threshold value to determine whether to (i) block an interrupt signal received from the first node from reaching the second node or (ii) allow the interrupt signal to reach the second node, an accumulator register stores the accumulator value, which is (i) increased whenever the first logic block allows an interrupt signal to reach the second node and (ii) otherwise periodically decreased, a summation node receives the accumulator value and one or more values that determine whether the accumulator value is to be increased or decreased, and a second logic block determines whether to increase or decrease the accumulator value based on whether an interrupt signal has been transmitted to the second processor.

Abstract: A system-on-chip (SoC) is disclosed. The SoC includes a set of input channels, a first partition including a set of output wrapper chains, a set of output channels, a second partition including a set of input wrapper chains, and an inter-partition circuit coupled between the first and second partitions. During an external test mode, the set of input channels receives input test data. The set of output wrapper chains receives and stores intermediate data that is generated based on the input test data. The inter-partition circuit receives the intermediate data from the set of output wrapper chains and generates test response data based on the intermediate data. The set of input wrapper chains receives the test response data, and provides the test response data to be captured as output test data at the set of output channels to test the inter-partition circuit.

Abstract: A system for controlling an inductor current of a boost converter includes a start-up controller that is configured to generate a control signal that has a fixed on-time duration and a dynamic off-time duration that decreases with each cycle of the control signal, and a pulse width modulation (PWM) circuit that is configured to generate a PWM signal. During a start-up of the boost converter, the PWM signal transitions from a deactivated state to an activated state when the control signal is activated, and from an activated state to a deactivated state when the inductor current is equal to a reference current. The reference current corresponds to a peak value of the inductor current during the start-up. Thus, during the start-up, the duty cycle of the PWM signal increases with each cycle of the PWM signal. The PWM signal is provided to the boost converter for controlling the inductor current.

Abstract: In accordance with a first aspect of the present disclosure, a system is provided for applying patches to executable codes, comprising: a plurality of execution environments configured to execute said codes in different execution contexts; a control unit configured to apply the patches to said codes; wherein the control unit is configured to apply a specific patch to a specific code upon or after an execution environment configured to execute said specific code switches to an execution context corresponding to said specific code. In accordance with other aspects of the present disclosure, a corresponding method is conceived for applying patches to executable codes, and a corresponding computer program is provided.

Abstract: Aspects of the present disclosure are directed toward effecting communications in a manner that suppresses side-channel communications that may otherwise cause interference. As may be implemented in a manner consistent with one or more aspects characterized herein, an apparatus and/or method involve transmitting enhanced signals for in-band transmissions over a first one of a plurality of wireless communications channels shared by a plurality of stations for communicating wireless station-to-station communications. While transmitting the enhanced signals, communications by legacy devices on a second one of the wireless communications channels adjacent the first channel are suppressed by generating and transmitting a side channel interference signal on the second channel, therein causing legacy devices receiving the enhanced signals to withhold communications on the second channel.

Abstract: An integrated grid cell on an integrated circuit (IC) is disclosed. The integrated grid cell corresponds to at least one of an integrated one-grid cell and an integrated two-grid cell. The integrated grid cell includes various polysilicon layers, metal-0 oxide diffusion (M0OD) layers, and a metal-0 polysilicon (M0PO) layer. The polysilicon layers, the M0OD layers, and the M0PO layer are formed such that potential differences are created between one or more polysilicon layers and one or more M0OD layers. Such potential differences between the one or more polysilicon layers and the one or more M0OD layers lead to formation of various parasitic capacitors between the one or more polysilicon layers and the one or more M0OD layers. The parasitic capacitors correspond to decoupling capacitors that mitigate a dynamic IR drop and a supply noise associated with the IC.

Abstract: An already deployed phased array can be calibrated in the near field without the need for an anechoic chamber or complex positioning mechanisms. Calibration includes positioning a transmitting antenna in the near field in front of the receiving antennas and generating range profiles while the transmitting antenna is positioned at various locations. The range profiles are utilized to produce various defined vectors that are then used in calculations that output a coupling calibration matrix and two vectors that compensate for receiver channel length and gain differences. The coupling calibration matrix and the vectors are input into the processing unit of the phased array in order to calibrate the receiving channels relative to each other.

Abstract: A regulator includes an error amplifier with a first input coupled to receive a reference voltage and a second input coupled to receive a feedback signal. A driver transistor provides an output voltage of the regulator that powers a memory. A replica transistor provides a replica voltage that powers a replica of the memory. A first ratio of a size of the replica of the memory to a size of the memory is less than one, and a second ratio of a drive strength of the replica transistor to a drive strength of the driver transistor is less than one. Each of the first ratio and the second ratio is at most 1/500. Switching circuitry provides one of the output voltage or the replica voltage as the feedback signal to the error amplifier.

Abstract: An integrated circuit is formed on a substrate, and the integrated circuit includes first and second conductors for providing supply and ground voltages, respectively, a clamp device, and a trigger circuit. The clamp device includes first and second metal oxide semiconductor (MOS) transistors coupled in series between the first and second conductors, wherein the first and second MOS transistors include first and second gates, respectively. The trigger circuit is coupled between the first and second conductors and is configured to drive the first and second gates with first and second voltages, respectively, in response to an electrostatic discharge (ESD) event. The trigger circuit includes a biasing circuit for generating the first voltage as a function of the supply voltage, a PMOS transistor coupled between the first conductor and the second gate, wherein the PMOS transistors includes a third gate.

Abstract: A RF switching arrangement (400) is described including a bias swap circuit (30). The bias swap circuit switches the bias voltage dependent on the state of the RF switch. This improves the performance of the RF switch without requiring charge pump circuitry.

Abstract: A controller for a switched mode power converter (SMPC) module for use in a multiphase SCMP is disclosed, comprising: a signal generator, configured to generate a periodic signal and a clock, both having a frequency and a signal phase, and for controlling the switched mode power converter module; a first-clock and second-clock inputs configured to receive respective first-clock and second-clock signal having the frequency and respective first and second phases from neighbouring controllers; and wherein the signal generator comprises a phase adjustment circuit configured to adjust the phase of the periodic signal so as to be equidistant from the first and second phase, wherein the phase adjustment circuit determines an error signal in dependence on an offset between the phase and a mid-point between the first phase and the second phase, and a feedback circuit configured to adjust the phase in dependence on the error signal.

Abstract: An integrated circuit is disclosed that includes a central processing unit (CPU), a random access memory (RAM) configured for storing data and CPU executable instructions, a first peripheral circuit for accessing memory that is external to the integrated circuit, a second peripheral circuit, and a communication bus coupled to the CPU, the RAM, the first peripheral circuit and the second peripheral circuit. The second peripheral circuit includes a first preload register configured to receive and store a first preload value, a first register configured to store first information that directly or indirectly identifies a first location where first instructions of a first task can be found in memory that is external to the integrated circuit, and a counter circuit that includes a counter value. The counter circuit can increment or decrement the counter value with time when the counter circuit is started. A first compare circuit is also included and can compare the counter value to the first preload value.

Abstract: One example discloses a magnetic induction device, including: a transmitter configured to induce a magnetic signal in a structure; wherein the structure is coupled to a sub-structure; a controller configured to characterize the structure so as to identify a first frequency range of the magnetic signal that resonates with the structure; wherein the controller is configured to identify a second frequency range that resonates with the sub-structure; wherein the controller is configured to select a frequency for the magnetic signal within the first frequency range that has a harmonic frequency in the second frequency range; and wherein the transmitter is configured to transmit the magnetic signal into the structure at the selected frequency.

Abstract: A radio frequency (RF) power transistor circuit includes a power transistor and a decoupling circuit. The power transistor has a control electrode coupled to an input terminal for receiving an RF input signal, a first current electrode for providing an RF output signal at an output terminal, and a second current electrode coupled to a voltage reference. The decoupling circuit includes a first inductive element, a first resistor, and a first capacitor coupled together in series between the first current electrode of the power transistor and the voltage reference. The decoupling circuit is for dampening a resonance at a frequency lower than an RF frequency.

Abstract: Aspects of the subject disclosure may include, for example, changing a tuning value of a tunable component coupled to an antenna from a first tuning value to a second tuning value during a first stage, and changing the tuning value of the tunable component from the second tuning value to a third tuning value during a second stage that occurs subsequent to the first stage, wherein during each of the first stage and the second stage the antenna is not utilized by a transmitter for communication purposes, wherein the first stage and the second stage are separated from one another by a first active region, and wherein during the first active region the transmitter causes a first signal to be transmitted from the antenna for communication purposes. Other embodiments are disclosed.