Abstract: A vehicle radar system, apparatus and method use a radar control processing unit generate compressed radar data signals, to apply the compressed radar data signals to a log detector to generate log detector sample values, and to generate a first log cell-average constant false alarm rate (CA-CFAR) threshold from the log detector sample values by computing and adding an average sample value SAVG from the log detector sample values, a probability of false alarm factor ?, and a log CA-CFAR correction factor ?, where the first log CA-CFAR threshold may be used with a second log CA-CFAR threshold to generate an ordered statistics CA-CFAR threshold for the compressed radar data signals by sorting the first and second log CA-CFAR thresholds by magnitude to form a sorted list of log CA-CFAR thresholds, and then selecting a kth threshold from the sorted list of log CA-CFAR thresholds as the OS-CA-CFAR threshold.

Abstract: Aspects of the subject disclosure may include, for example, changing a tuning value of a tunable component coupled to an antenna from a first tuning value to a second tuning value during a first stage, and changing the tuning value of the tunable component from the second tuning value to a third tuning value during a second stage that occurs subsequent to the first stage, wherein during each of the first stage and the second stage the antenna is not utilized by a transmitter for communication purposes, wherein the first stage and the second stage are separated from one another by a first active region, and wherein during the first active region the transmitter causes a first signal to be transmitted from the antenna for communication purposes. Other embodiments are disclosed.

Abstract: A system-on-chip (SoC) includes a system memory, a memory controller, and a memory management system coupled therebetween. The memory management system is configured to receive, from the memory controller, a first control signal that is indicative of a memory operation associated with the system memory, and output and provide a second control signal to the system memory to control an execution of the memory operation. The second control signal is outputted such that when the memory operation corresponds to a first read operation, the first read operation is executed with the system memory, and when the memory operation corresponds to a first write operation, a second read operation is executed with the system memory followed by the first write operation. Thus, the memory management system prevents memory corruption of the system memory when an asynchronous reset event is detected in the SoC.

Abstract: A first communication device generates and transmits a first physical layer (PHY) data unit as part of a hybrid automatic repeat request (HARQ) session, the first PHY data unit having a first plurality of media access control (MAC) protocol data units (MPDUs) including a first MPDU. The first communication device determines that a second communication device did not acknowledge successfully receiving the first MPDU. The first communication device generates and transmits a second PHY data unit as part of the HARQ session, the second PHY data unit having a second plurality of MPDUs, the second plurality of MPDUs including the first MPDU.

Abstract: Operating a wireless communications network includes transmitting a management frame by a first multi-link entity of a set of entities using a reporting link associated with a first network identifier and a first communication band. The management frame includes first information associated with the first multi-link entity and second information associated with a second link of the set of entities. The second link is associated with a second network identifier.

Abstract: A purification apparatus includes a radio frequency (RF) signal source that generates an RF signal, first and second electrodes, and a conduit. The first electrode receives the RF signal and converts it into electromagnetic energy that is radiated by the first electrode. The conduit includes input and output ports and a chamber. The input and output ports are in fluid communication with the chamber, and the chamber is configured to receive an electrodeless bulb. The chamber is defined by first and second boundaries that are separated by a distance that is less than the wavelength of the RF signal so that the chamber is sub-resonant. The first electrode is physically positioned at the first boundary, and the second electrode is physically positioned at the second boundary. The first and second electrodes and the chamber form a structure that capacitively couples the electromagnetic energy into an electrodeless bulb within the chamber.

Abstract: Testing of integrated circuitry, wherein the integrated circuitry includes a flip-flop with an asynchronous input, so that during performance of asynchronous scan patterns, glitches are avoided. Combinatorial logic circuitry delivers a local reset signal to the asynchronous input independent of an assertion of an asynchronous global reset signal. A synchronous scan test is performed of delivery of the local reset signal from the combinatorial logic circuitry while masking delivery of any reset signal to the asynchronous input of the flip-flop. An asynchronous scan test is performed of an asynchronous reset of the flip-flop with the asynchronous global reset signal while masking delivery of the local reset signal to the asynchronous input of the flip-flop.

Abstract: An apparatus includes front-end circuitry to receive radar wave signals and a fast fourier transforms (FFT) signal processor. The FFT signal processor includes multiplication logic circuitry and other logic circuitry. The FFT signal processor derives doppler information from the radar wave signals by operating on a digital stream of input data representing the radar wave signals including using the multiplication logic circuitry to perform multiplication operations on first data in the digital stream while the first data is represented in a signed magnitude form, and using the other logic circuitry to perform other mathematical operations on second data in the digital stream while the second data is represented in a two's complement form.

Abstract: Radio frequency (RF) power dies having flip-chip architectures are disclosed, as are power amplifier modules (PAMs) containing such RF power dies. Embodiment of the PAM include a module substrate and an RF power die, which is mounted to a surface of the module substrate in an inverted orientation. The RF power die includes, in turn, a die body having a frontside and an opposing backside, a transistor having active regions formed in the die body, and a frontside layer system formed over the die body frontside. The frontside layer system contains patterned metal layers defining first, second, and third branched electrode structures, which are electrically coupled to the active regions of the transistor. A frontside input/output interface is formed in an outer terminal portion of the frontside layer system and contains first, second, and third bond pads electrically coupled to the first, second, and third branched electrode structures, respectively.

Abstract: Embodiments of a gain control circuit and a wideband communication circuit that uses the gain control circuit are disclosed. In an embodiment, gain control circuit includes first and second output terminals to output gain control signals and first and second diode-connected transistors connected between a supply voltage and the first and second output terminals, which are connected to input terminals of a communication component circuit with a plurality of input transistors. The gain control circuit further includes a current digital-to-analog converter connected to the diode-connected transistors to generate first and second currents for the diode-connected transistors based on an N-bit input code, wherein a ratio of the first and second currents sets voltages of the gain control signals that are output from the gain control circuit to the communication component circuit to control signal gain provided by the communication component circuit.

Abstract: Embodiments of a method, a circuit and a system are disclosed. In an embodiment, a discharge protection circuit is disclosed. The discharge protection circuit includes a switch having a capacitive coupling between a gate and a drain of the switch, wherein the capacitive coupling facilitates a capacitively coupled current. The discharge protection circuit further includes a gate network including at least the gate of the switch, a gate control element and a resistor connected to the gate and the gate control element. In addition, the discharge protection circuit includes an electrostatic discharge rail that connects to a diode that is coupled to the gate and the resistor, wherein the capacitive coupling facilitates sinking of at least a part of an electrostatic discharge current via the gate network.

Abstract: Embodiments of a device and method are disclosed. In an embodiment, a method of communications involves determining a time-division multiplex (TDM) communications schedule over an asymmetrical point-to-point link and at a communications device, transmitting or receiving data according to the TDM communications schedule over the asymmetrical point-to-point link. The TDM communications schedule specifies multiple non-overlapping transmission time slots for different communications devices and a silent period for echo fade-out between consecutive transmission time slots of the non-overlapping transmission time slots.

Abstract: A power-on reset circuit includes a complementary-to-absolute-temperature circuit that outputs one control voltage, and a proportional-to-absolute-temperature (PTAT) circuit that outputs a PTAT current. The power-on reset circuit further includes various resistors that are coupled in series, and generate another control voltage based on the PTAT current that is outputted by the PTAT circuit. Further, the power-on reset circuit includes a comparator that compares the two control voltages to generate a power-on reset signal. The power-on reset signal is activated when a supply voltage is greater than or equal to a trip voltage, and deactivated when the supply voltage is less than the trip voltage. A functional circuit is configured to execute a reset operation associated therewith when the power-on reset signal transitions from a deactivated state to an activated state.

Abstract: A multi-branch analog multiplexer (anamux) includes protection circuitry to help dissipate both positive and negative injected current without increasing the size of hardening transistors in each branch, thereby avoiding increased leakage current and enabling an analog to digital converter to operate with the required accuracy. The protection circuitry is tied to the body of the hardening transistor to lower the threshold voltage of the hardening device, thereby enabling the hardening device to handle more of the injected current.

Abstract: A system, method, and apparatus are provided for processing packets received over Controller Area Network (CAN) interface where a CAN protocol controller computes a CRC value from header and payload values in a received CAN data frame to verify frame integrity of the received CAN data frame across a physical media layer, and then stores the header and payload values and the CRC value in a memory buffer of the CAN protocol controller so that a host core can compute a reconstructed CRC value from the header and payload values retrieved from the memory buffer, and then compare the reconstructed CRC value to the CRC value retrieved from the memory buffer to verify frame integrity of the received CAN data frame at a transaction layer.

Abstract: In generating a physical layer (PHY) data unit is for transmission in a shared communication medium during a transmit opportunity (TXOP), a wireless communication device generates a TXOP field to indicate a length of time remaining in the TXOP. The wireless communication device generates a physical layer (PHY) preamble of the PHY data unit to include a legacy signal field in a legacy portion of the PHY preamble and a non-legacy signal field in a non-legacy portion of the PHY preamble, the non-legacy signal field generated to include the TXOP field. The wireless communication device generates the PHY data unit to include the PHY preamble and a data portion, and transmits the PHY data unit in the shared communication medium.

Abstract: In accordance with a first aspect of the present disclosure, a transponder is provided, comprising: a field strength range determination unit configured to determine a field strength range of a radio frequency (RF) field generated by an external reader device; a controller configured to delay processing of a command by the transponder in dependence on the field strength range determined by the field strength range determination unit. In accordance with further aspects of the present disclosure, a corresponding method of operating a transponder is conceived, and a corresponding computer program is provided.

Abstract: One example discloses a device for electromagnetic structural characterization, including: a controller having an electromagnetic transmitter output and a communications interface; wherein the controller is configured to send a signal over the electromagnetic transmitter output that causes an electromagnetic transmitter to generate a first electrical field (E1) and a first magnetic field (H1); wherein the controller configured to receive over the communications interface a second electric field (E2) and a second magnetic field (H2) received by an electromagnetic receiver; wherein the first electrical field and the first magnetic field correspond to when the electromagnetic transmitter is at a first location proximate to a structure and the second electrical field and the second magnetic field correspond to when the electromagnetic receiver is at a second location proximate to the structure; and wherein the controller is configured to calculate an impedance based on the electric and magnetic fields interacting

Abstract: A processing system including a memory, command sequencers, accelerators, and memory banks. The memory stores program code including instruction threads sequentially listed in the program code. The command sequencers include a master command sequencer and multiple slave command sequencers. The master command sequencer executes the program code including distributing the instruction threads for parallel execution among the slave command sequencers. The instruction threads may be provided inline or accessed via inline thread line pointers. Each accelerator is available to each command sequencer in which multiple command sequencers may access multiple accelerators for parallel execution. The memory banks are simultaneously available to multiple accelerators. The master command sequencer may perform implicit synchronization by waiting for completion of simultaneous execution of multiple instruction threads. A command sequencer arbiter may arbitrate among the command sequencers.

Abstract: Embodiments provide line-based feature generation for vision-based driver assistance systems and methods. For one embodiment, a feature generator includes a circular buffer and a processor coupled to an image sensor. The circular buffer receives image data from the image sensor and stores N lines at a time of an image frame captured by the image sensor. The N lines of the image frame are less than all of the lines for the image frame. The processor receives the N lines from the circular buffer and stores one or more features generated from the N lines in a memory. Iterative blocks of N lines of image data are processed to complete processing of the full image frame, and multiple frames can be processed. The generated features are analyzed by a vision processor to identify, classify, and track objects for vision-based driver assistance and related vision-based assistance actions.