Abstract: One example discloses a near-field wireless device, including: a stack of layers distributed along a first axis; a first near-field antenna having a conductive surface and embedded in a first layer within the stack of layers; wherein the conductive surface is configured to carry non-propagating quasi-static near-field electric-induction signals for on-body near-field communications; a second near-field antenna having an inductive loop and embedded in a second layer within the stack of layers; wherein the inductive loop is configured to carry non-propagating quasi-static near-field magnetic-induction signals for off-body near-field communications; wherein the first and second layers are different layers; and wherein the first and second antennas are not in galvanic contact.

Abstract: A wireless battery charging system includes a trickle power device (e.g., FET) that generates a trickle charging current for charging a battery and a trickle charging regulator that controls the trickle power device. A fast charging device generates a fast charging current for charging the battery, where the fast charging current is greater than the trickle charging current. A fast charging regulator controls the fast charging device. A digital control module generates a trickle charging codeword to control the trickle charging regulator and a fast charging codeword to control the fast charging regulator. Each charging regulator has a programmable current mirror that generates a mirrored current signal based on a codeword from the digital control module. The digital control module instructs the charging regulators to control the power devices to operate in a trickle charging mode, a fast charging mode, and transitions between those modes.

Abstract: A chip for securing storage of information includes a manager to access a pointer and a cipher engine to decrypt stored data. The pointer includes a first area and a second area. The first area includes an address indicating a storage location of the data and the second area includes a safety tag. The cipher engine decrypts the data output from the storage location based on a key and the safety tag in the second area of the pointer. These and other operations may be performed based on metadata that indicate probabilities that a correct safety tag was used to decrypt the data. In another embodiment, the manager may be replaced with an L1 cache.

Abstract: An example apparatus includes power amplification circuitry and current-level switch circuitry. The power amplification circuitry has a first input port, a second input port, and field-effect transistor (FET) circuitry, the FET circuitry to operate in a saturation mode while drawing power provided at the first input port from a first power source. The current-level switch circuitry is to sense a change in a current-level used to maintain the FET circuitry in the saturation mode and, in response to the sensed change in the current-level, to cause the power amplification circuitry to draw power provided at the second input port from a second power source while maintaining the saturation mode of the FET circuitry.

Abstract: There are disclosed fault detection circuits and methods for an N-to-1 Dickson topology hybrid DC-DC power converter. A short circuit fault detection circuit comprises: first and second measuring circuits configured to measure first and second voltages, Vsw1, Vsw2, at the switching node in the first and second state; first and second calculation circuits configured to calculate first and second absolute error voltage as an absolute difference of the respective first and second voltages in one operating cycle (Vsw1[n?1], Vsw2[n?1]) and in a next subsequent operating cycle (Vsw1[n], Vsw2[n]); and first and second fault circuits configured to provide first and second fault outputs indicative of a fault in response to the respective first or second absolute error voltage exceeding a short-circuit-trip level. Open circuit fault detection circuits and methods are also disclosed.

Abstract: A voltage regulator circuit comprises a regulator output; an amplifier that is activated in response to a first signal and inactivated in response to a second signal, the error amplifier having a first input for receiving a reference voltage, a second input for receiving a feedback voltage, and an output that generates a differential with respect to the reference voltage and the feedback voltage; an active discharging transistor that, in response to a falling slope of the electronic signal, discharges a present electronic signal at the regulator output; and a first switch at the output of the amplifier that is in open state in response to a receipt of the second signal to disconnect a coupling capacitor path between the regulator output and the reference voltage to negate an effect of noise on the reference voltage in response to the falling slope of the electronic signal.

Abstract: An example apparatus is for use with an electronic circuit breaker having a plurality of current paths connected between a connection terminal to a power source and a load terminal. The apparatus includes power access circuitry and control circuitry. The power access circuitry monitors circuit access of power via the power source by modulating use of the plurality of current paths of the electronic circuit breaker while assessing actual usage of the power source via a power-related parameter relative to expected usage of the power source. The control circuitry responds to the assessment by generating a signal indicative of a diagnostic result associated with operation of the electronic circuit breaker.

Abstract: An integrated circuit that can include a driver having a first driver output, and a first resistance coupled between a first node coupled to the first driver output and a second node. The first resistance can include a process resistor including a first material having a first temperature coefficient, and an interconnect resistor configured to provide at least 20% of the first resistance and including a second material having a second temperature coefficient which changes resistance in an opposite direction with temperature as compared to the first temperature coefficient. A first terminal of the interconnect resistor is directly connected to a first terminal of the process resistor.

Abstract: Embodiments of a linear equalizer are disclosed. In an embodiment, a linear equalizer includes a plurality of input transistors, a plurality of gain control transistors and first and second impedance elements. The plurality of input transistors is connected to input terminals of the linear equalizer to receive input signals. The plurality of gain control transistors is connected between a supply voltage and the plurality of input transistors. The plurality of gain control transistors is also connected to gain control terminals to receive gain control signals. At least some of the gain control transistors are connected to output terminals of the linear equalizer to transmit output signals. The first and second impedance elements are connected between at least some of the input transistors and at least one fixed voltage. A peaking gain of the linear equalizer is defined by gain control signals applied to the gain control terminals.

Abstract: A method and apparatus are described for OTP control logic with randomization for sensing and writing fuse values. In an embodiment, OTP control logic has an address counter to determine an address of a fuse to be read from an OTP fuse box and a corresponding address of a shadow register, a fuse box addressing circuit to read a fuse value from a fuse of the fuse box, a clock circuit coupled to the address counter to provide a clock signal to the address counter, and a randomization circuit to interrupt the clock signal at random times to prevent the address counter from determining a next address in response to the clock signal.

Abstract: A methodology and apparatus are disclosed for providing standby power during standby mode by applying a low frequency sampling clock signal to first and second comparators which are connected to compare an output voltage generated at an external capacitor to, respectively, a first higher voltage threshold and a second lower voltage threshold, where the first comparator generates an enable signal in response to the output voltage reaching the first higher voltage threshold for use in activating one or more switched regulator circuits to pump up the output voltage at the external capacitor to exceed the first higher voltage threshold, and where the second comparator generates an undervoltage signal in response to the output voltage reaching the second lower voltage threshold for use in reactivating the main regulator to pump up the output voltage at the external capacitor to exceed the first higher voltage threshold.

Abstract: A mechanism is provided to determine if a short-range automotive radar detection is a direct reflection or an indirect (also known as “multipath”) reflection from a physical target object. The multipath information is further used to perform a height estimation of the object. Embodiments provide a radar system having a range resolution smaller than a path difference between the direct reflection path and the indirect reflection path. Both range separation techniques and Doppler separation techniques are utilized to provide a reliable and accurate estimation of the height of the object.

Abstract: An n-well voltage switching circuit (60) and methodology are disclosed for generating a maximum bias voltage (VMAX) at the output voltage node with cross-coupled PMOS switching transistors (63) connected to a voltage supply remapping circuit (61, 62, 64) which receives first and second power supplies (VSUP1, VSUP2) and generates first and second gate driving signals (G1, G4), wherein the first and second gate driving signals are connected, respectively, to the gates of the first and second cross-coupled PMOS transistors (P5, P6) to pull a gate for one of the cross-coupled PMOS transistors to ground so that the higher of the first and second power supplies is coupled to the output voltage node over one of the first and second cross-coupled PMOS transistors, thereby generating a maximum bias voltage at the output voltage node.

Abstract: Embodiments of active baluns are disclosed. In an embodiment, an active balun includes input terminals configured to receive a single-ended input signal and a linear redriver configured to transform the single-ended input signal into a differential output signal.

Abstract: A non-volatile memory includes virtual ground circuitry configured to generate a virtual ground voltage at a virtual ground node, a memory array of memory cells in which each memory cell includes a select transistor and a storage element and is coupled to a first column line of a plurality of first column lines; and a first decoder configured to select a set of first column lines for a memory write operation to a selected set of the memory cells. The non-volatile memory also includes write circuitry configured to receive a write value for storage into the selected set of memory cells, and a first column line multiplexer configured to, during the memory write operation, couple each selected first column line of the set of first column lines to the write circuitry, and couple each unselected first column line of the plurality of first column lines to the virtual ground node.

Abstract: An electric motor drive apparatus comprising a voltage converter component arranged to receive a supply voltage signal and output a bus voltage signal, and a motor driver component arranged to receive the bus voltage signal and generate at least one drive signal for an electric motor from the bus voltage signal. The motor driver component is arranged to output a bus voltage feedback signal to the voltage converter component. The voltage converter component is arranged to regulate a voltage level of the bus voltage signal based at least partly on the bus voltage feedback signal output by the motor driver component.

Abstract: A radar system, apparatus, architecture, and method are provided for generating a difference co-array virtual aperture by using a radar control processing unit to coherently combine virtual array apertures from multiple small aperture radar devices to construct a sparse MIMO virtual array aperture and to construct an extended difference co-array virtual array aperture that is larger than the MIMO virtual array aperture by using an FFT hardware accelerator to perform spectral-domain auto-correlation based processing of the sparse MIMO virtual array aperture to fill in holes in the sparse MIMO virtual array aperture and to suppress spurious sidelobes caused by holes in the sparse MIMO virtual array aperture.

Abstract: A self-test mechanism within an integrated circuit to test for faulty operation of a clock monitor unit implemented within the integrated circuit for monitoring a clock signal. The mechanism intentionally injects faults into the clock monitor unit to evaluate if the clock monitor unit is operating in accordance with its specified operating parameters. The injected faults are intended to cause the clock monitor unit to determine that the clock signal is operating outside of an artificially generated, imaginary specified frequency range. If the injected faults do not cause the clock monitor unit to determine that the clock signal is operating both above and below the artificially generated, imaginary specified frequency range, then the clock monitor unit is not functioning according to specified operating parameters.

Abstract: A self-test mechanism within an integrated circuit to automatically interleave evaluation of a clock signal by a clock monitor unit with periodic testing for faulty operation of a clock monitor unit implemented within the integrated circuit for monitoring a clock signal. The mechanism injects faults into the clock monitor unit to evaluate if the clock monitor unit is operating in accordance with its specified operating parameters. The injected faults are intended to cause the clock monitor unit to determine that the clock signal is operating outside of a specified frequency range. If the injected faults do not cause the clock monitor unit to determine that the clock signal is operating both above and below the specified frequency range, then the clock monitor unit is not functioning according to specified operating parameters.

Abstract: A transistor device having a channel region including a portion located in a sidewall of semiconductor material of a trench and an extended drain region including a portion located in a lower portion of the semiconductor material of the trench. In one embodiment, a control terminal of the transistor device is formed by patterning a layer of control terminal material to form a sidewall in the trench and a field plate for the transistor device is formed by forming a conductive sidewall spacer structure along the sidewall of the control terminal material.