Abstract: The embodiments described herein include amplifiers that are typically used in radio frequency (RF) applications. Specifically, the amplifiers described herein include a phase distortion compensation circuit that can compensate for input impedance variations that could otherwise lead to reduced efficiency and power performance. In one specific embodiment, the phase distortion compensation circuit is used to compensate for input impedance variations in the peaking amplifiers of a Doherty amplifier. In such embodiments, the phase distortion compensation circuit can absorb the non-linear input impedances of the peaking amplifiers in a way that may facilitate improved phase maintenance between the carrier and peaking stages of the Doherty amplifier.

Abstract: A data transmission interface for use in a first integrated circuit, for encoding and sending a data packet from the first IC to a second IC via a data bus having three data wires, the data transmission interface being arranged to generate three time-dependent binary signals which jointly encode the data packet, each of the signals being associated with a unique data wire of the data bus and spanning a temporal cycle T within which are defined six consecutive time stamps T1 . . . T6 at which the signals are allowed to change logical state, the data transmission interface further arranged to transmit the signals to the second IC substantially in parallel on their respective data wires, wherein, irrespective of the data packet content: at each time stamp T1 . . .

Abstract: A single-stage voltage clamp device with high holding voltage characteristics (e.g., ˜40V) includes two p-n-p structures coupled in series via an n-p-n structure. The device has a low-voltage terminal that may be coupled to the ground of a circuit and high voltage terminal that may be coupled to a voltage source of the circuit. A highly doped floating (n+)/(p+) junction region within a heavily doped base of the low-voltage-side p-n-p structure allows for holding voltages of at least 40V in the single-stage device without the need to employ two such devices in series to achieve the desired holding voltage.

Abstract: One specific example involves an integrated circuit that has application logic circuitry which includes flip-flop circuits susceptible to degradations of setup and hold times relative to specified minimum setup and hold times for signals to be processed by the respective flip-flop circuits. In a method carried out by the integrated circuit, timing-based logic states of the flip-flop circuits are controlled, based on at least one transition-scan pattern processed by the flip-flop circuits as part of the application logic circuitry; and respective logic states are set for those flip-flops, which due to degradations of the actual setup and hold times do not satisfy anymore the originally specified minimum setup and hold times.

Abstract: An integrated circuit includes a signal pad, an output buffer having an output coupled to the signal pad and having an enable input, an input buffer having an input coupled to the signal pad and having an enable input, a counter, and a gating circuit. The counter is enabled to start counting down a predetermined count value when a voltage on the signal pad is both higher than a predetermined low threshold voltage and lower than a predetermined high threshold voltage, wherein the predetermined low threshold voltage corresponds to a threshold below which a voltage corresponds to a logic level zero and the predetermined high threshold voltage corresponds to a threshold above which a voltage corresponds to a logic level one. The gating circuit is configured to, in response to the counter expiring, disable the input buffer and the output buffer.

Abstract: A chirp linearity detector, integrated circuit, and method are provided. The chirp linearity detector comprises a phase-locked loop (PLL) frequency sampling circuit and a frequency sweep linearity measuring circuit. The PLL frequency sampling circuit comprises a frequency divider circuit for receiving a PLL output signal from a PLL and for providing a frequency divided output signal, a first low pass filter circuit for receiving the frequency divided output signal, for reducing harmonic mixing, and for providing a mixer input signal, a mixer circuit for receiving the mixer input signal, for mixing the mixer input signal with a local oscillator signal, and for providing a mixer output signal, a second low pass filter circuit for performing anti-aliasing filtering and for providing an analog-to-digital converter (ADC) input signal, and an ADC circuit for digitizing the ADC input signal and for providing a digital output signal.

Abstract: A method for controlling a multiphase synchronous motor, for a motor flux vector includes setting a first winding of the motor to a floating state in which the first winding is electrically floating; setting a voltage across a second winding of the motor for a first period; receiving first voltage samples associated with the first winding in the first period; setting the voltage across the second winding to a second period, in which the first period and the second period are periods of one or more pulse width modulation cycles, in which a polarity of the voltage across the second winding in the second period is opposite to a polarity of the voltage across the second winding in the first period; receiving second voltage samples associated with the first winding in the second period; and determining a position of the rotor based on the first and second voltage samples.

Abstract: Integrated circuitry, such as a microcontroller, for controlling an electric motor includes circuitry for measuring a bi-directional current flowing within a coil of the electric motor. The current is sensed by an externally implemented current sensing element, such as a shunt resistor, to produce a differential voltage that is delivered to input pins of the microcontroller, which are protected by electrostatic discharge protection circuits. Current sources implemented within the microcontroller are coupled to the input pins, and work in concert with external resistors to shift the differential voltage so that it is maintained within an appropriate voltage operating range so that an accurate measurement of the bi-directional current can be made by the microcontroller.

Abstract: A WLAN Access Point (AP) includes a MAC processor and a PHY processor. The MAC processor is configured to generate a trigger frame including user information fields destined to respective STAs, and a padding field including one or more padding bits, to determine a number of padding bits that, after the trigger frame including the padding bats being encoded for transmission, satisfy a processing-time constraint imposed by the STAs, and to insert the determined number of padding bits in the padding field. The PHY processor is configured to generate a packet from the trigger frame, including encoding the trigger frame in accordance with an ECC, into one or more code words whose length depends on a number of padding bits in the padding field, to generate multiple modulated symbols from the one or more code words of the packet, and to transmit the modulated symbols to the STAs.

Abstract: A software only debug approach is provided that does not require special hardware in a target embedded system undergoing debug. Instead, already present DMA capabilities of the target system are utilized to transfer I/O operation parameters into a memory area accessible to both the target processor and a debugger executing on a host system. The debugger can thereby access and execute the I/O operations without program execution stopping on the target. A semihosting library is provided as a replacement for the standard C I/O library on the target. The semihosting library provides a range of equivalent functions to the standard C I/O API that program a DMA transfer to copy the I/O function parameters to an external memory area that is not otherwise being used by the target core processor. The external memory area is then accessed by a debug tool on the host computer.

Abstract: A method for communication in a wireless local area network (WLAN) includes receiving, at first and second access points (APs) in the WLAN, uplink signals from a first client station (STA), which is associated with a basic service set (BSS) of the first AP. First downlink signals are transmitted from the first AP to the first STA using a first steering matrix. Responsively to the received uplink signals, a second steering matrix is computed, having a null in a direction of the first STA. Second downlink signals are transmitted from the second AP to a second STA in the WLAN using the second steering matrix.

Abstract: A method for Wireless Local-Area Network (WLAN) communication in a WLAN device includes generating a WLAN transmission including first bits, by at least (i) encoding the first bits with a Forward Error Correction (FEC) code to produce first encoded bits, and (ii) scrambling the first encoded bits with a first scrambling sequence. The WLAN transmission is transmitted from the WLAN device to a remote WLAN device. In response to receiving from the remote WLAN device an indication that reception of the WLAN transmission has failed, a WLAN retransmission including second bits is generated. Generating the retransmission includes (i) obtaining second encoded bits, which include the second bits encoded with the FEC code, and (ii) scrambling the second encoded bits with a second scrambling sequence that is different from the first scrambling sequence. The WLAN retransmission is transmitted from the WLAN device to the remote WLAN device.

Abstract: A fast chirp Phase Locked Loop with a boosted return time includes a Voltage Controlled Oscillator, VCO, generating a Frequency Modulated Continuous Waveform, FMCW. The VCO responds to a filtered output voltage of a filter connected to a charge pump. A digital controller modifies the FMCW to generate a chirp phase and a return phase. The chirp phase includes a first linear change of the FMCW from a start frequency to a stop frequency. The return phase includes a second linear change of the FMCW from the stop frequency to the start frequency. A boost circuit connects to the digital controller and the filter. The boost circuit supplies a boost current during the return phase. The boost current is proportional to a return slope of the return phase and inversely proportional to a VCO gain of the VCO.

Abstract: An access point receives a first uplink orthogonal frequency division multiple access (OFDMA) transmission from a plurality of client stations. The first uplink OFDMA transmission includes i) respective acknowledgment frames for the downlink OFDMA PHY data unit, and ii) respective frames that include indications of respective amounts of buffered data at the respective client stations that are to be transmitted to the access point. The access point uses the received indications of respective amounts of buffered data at the respective client stations to determine an allocation of frequency resources for a second uplink OFDMA transmission, and transmits a second downlink OFDMA PHY data unit to the plurality of client stations, which i) indicates the allocation of frequency resources to the plurality of client stations for the second uplink OFDMA transmission, and ii) is configured to prompt the plurality of client stations to begin transmitting the second uplink OFDMA transmission.

Abstract: An ESD protection device including a PNP transistor connected to an input pad, a diode connected to the PNP transistor and connected to an output pad, and an NMOS transistor connected to the PNP transistor and the output pad, wherein the diode, PNP transistor, and NMOS transistor are configured to route different levels of an electrostatic discharge (ESD) current pulse from the input pad to the output pad.

Abstract: A fast chirp Phase Locked Loop with a phase preset includes a Voltage Controlled Oscillator, VCO, generating a Frequency Modulated Continuous Waveform, FMCW. The VCO responds to a filtered output voltage of a filter connected to a charge pump. A digital controller modifies the FMCW to generate a chirp phase and a return phase. The chirp phase includes a first linear change of the FMCW from a start frequency to a stop frequency. The return phase includes a second linear change of the FMCW from the stop frequency to the start frequency. A phase preset circuit connects to the digital controller and the filter. The phase preset circuit supplies a phase preset current during a start frequency time preceding the chirp phase. The phase preset current is proportional to a VCO gain of the VCO and inversely proportional to a chirp current during the chirp phase.

Abstract: A mechanism is provided to reduce a distance of a waveguide antenna from transmit and receive circuitry in an integrated circuit device die. This distance reduction is performed by providing vertical access to radio frequency connections on a top surface of the IC device die. A cavity in the encapsulant of the package can be formed to provide access to the connections and plated to perform a shielding function. A continuous connection from the RF pads is used as a vertical interconnect. The region around the vertical interconnect can be filled with encapsulant potting material and back grinded to form a surface of the semiconductor device package. A waveguide antenna feed can be plated or printed on the vertical interconnect on the surface of the package.

Abstract: A method of manufacturing a semiconductor device is provided. The method includes forming an assembly including placing a semiconductor die and a launcher structure on a carrier substrate, encapsulating at least a portion of the semiconductor die and the launcher structure, and applying a redistribution layer on a surface of the semiconductor die and a surface of the launcher structure to connect a bond pad of the semiconductor die with an antenna launcher of the launcher structure. The assembly is attached to a substrate and a waveguide overlapping the assembly is attached to the substrate. The waveguide structure is physically decoupled from the assembly.

Abstract: One example discloses an organic matter powered device, comprising: a set of electrodes configured to be coupled to a set of biologically active organic matter; a power generation circuit coupled to the electrodes; wherein the power generation circuit is configured to receive a first voltage and current from the organic matter, and output a second voltage and current generated by the first voltage and current; a monitoring circuit coupled to the electrodes and coupled to monitor the first voltage and current, and to be powered by the second voltage and current; wherein the monitoring circuit is configured to translate variations in the first voltage and current into an environmental attribute.

Abstract: A radio frequency (RF) switch circuit is provided. The switch includes a branch configured and arranged to transfer an RF signal coupled at an input node to an output node when a control signal is at a first logic value. A first transistor in the branch includes a first current electrode coupled at the input node and a second current electrode coupled to an intermediate node. The first transistor is formed in a first isolation well coupled to a bias voltage supply terminal. A second transistor in the branch includes a first current electrode coupled to the second current electrode of the first transistor at the intermediate node and a second current electrode coupled at the output node. The second transistor is formed in a second isolation well coupled to the bias voltage supply terminal. A third transistor includes a first current electrode coupled at the first intermediate node and a second current electrode coupled at a first supply terminal.