Patents Assigned to NXP
  • Patent number: 11175977
    Abstract: A method, system, apparatus, and architecture are provided for detecting failure of a PCIe endpoint device by scanning an extended configuration space for each connected PCIe endpoint device to detect a first PCIe endpoint device that supports advance status reporting, and then by programming a first predetermined value and a second predetermined value, respectively, into an endpoint response register and a root complex request register of a dedicated memory control word in the extended configuration space for the first PCIe endpoint device, where the second predetermined value signals a request to the first PCIe endpoint device to update the endpoint response register of the dedicated memory control word with a new status value so that, after a minimum specified delay, a report that the first PCIe endpoint device has failed may be generated in response to detecting that the first predetermined value is stored in the endpoint response register.
    Type: Grant
    Filed: January 14, 2020
    Date of Patent: November 16, 2021
    Assignee: NXP USA, Inc.
    Inventors: Udit Kumar, Varun Sethi, Prabhjot Singh, Wasim Khan
  • Patent number: 11177729
    Abstract: A method and system are provided for supplying power with an LDO linear voltage regulator (110) having an LDO power supply (114, 115) and a load switch (116) by connecting a power supply voltage (102, 104) to a main core (121) and a standby core (122) in a multi-core low power microcontroller (120) during an active mode so that the standby core receives a first supply voltage that tracks the power supply voltage during the active mode, and upon detecting a standby mode for the multi-core low power microcontroller, disconnecting the power supply voltage from the standby core and connecting a low dropout (LDO) linear power supply voltage to the standby core during the standby mode so that the standby core receives the LDO linear power supply voltage as a second supply voltage during the standby mode.
    Type: Grant
    Filed: April 16, 2019
    Date of Patent: November 16, 2021
    Assignee: NXP USA, Inc.
    Inventors: Alaa Eldin Y El Sherif, Keith Jackoski, Neal G. Baltz, Ruchika Pandya, Bo Wu
  • Patent number: 11177210
    Abstract: An integrated circuit includes functional structures and non-functional structures. The functional structures include one or more functional metal structures. The non-functional structures include one or more non-functional metal structures. At least one of the one or more non-functional metal structures is connected to at least one of the one or more functional metal structures. For example, the at least one non-functional metal structure is connected to the at least one functional metal structure through a via. Alternatively, the at least one non-functional metal structure is connected to the at least one functional metal structure by physically contacting the at least one functional metal structure without using a via.
    Type: Grant
    Filed: December 31, 2019
    Date of Patent: November 16, 2021
    Assignee: NXP B.V.
    Inventors: Sven Trester, Tobias Richard Erich Nink
  • Patent number: 11176254
    Abstract: Disclosed are various embodiments for implementing automatic firmware rollbacks after a configured number of attempts to execute the latest firmware update associated with an electronic computing unit have occurred. In a computing device, such as an electronic computing unit, a watchdog automatically generates a system reset in response to a software fault. A reset counter is configured to count a number of system resets generated by the watchdog. In response to the occurrence of the watchdog, a configurable threshold value associated with a threshold data record is compared with the value associated with the reset counter. In response to a determination that the threshold value associated with the threshold data record is greater than or equal to the value associated with the reset counter, a rollback application is executed such that the rollback application performs a swap of a first version of a firmware with a second version of the firmware.
    Type: Grant
    Filed: July 3, 2019
    Date of Patent: November 16, 2021
    Assignee: NXP USA, Inc.
    Inventors: Stefan Singer, Osvaldo Israel Romero Cortez, Guillaume Perret
  • Patent number: 11175779
    Abstract: In connection with a touch indicating array device, exemplary aspects concern, a method involving the device having a touch surface and an array of sensors used to indicate a rough or coarse position, when touched, via a numeric value vector. This vector's weighted values may indicate the effective touch at each of the sensor position of the touch device. The weighted values may be processed by a module which operates on the weighted values using a discrete transform for obtaining one or more harmonic's phase of the spectral representation of the sensor array values. The resultant phase value of the first harmonic, representing a spatial phase, may then be used to refine the position within the sensor array that is more accurate than the rough or course position.
    Type: Grant
    Filed: December 18, 2020
    Date of Patent: November 16, 2021
    Assignee: NXP USA, Inc.
    Inventors: David Pamanek, Petr Zelinka
  • Patent number: 11175691
    Abstract: A method for optimizing power of a ranging sequence includes counting at least one cycle of a first clock during a Crystal Oscillator (XO)-mode to generate a first cycle count. A second clock is activated at an end of the XO-mode. The first cycle count is converted into a fractional correction value by multiplying the first cycle count by a ratio of a second period of the second clock divided by a first period of the first clock. A first alignment of the first clock to the second clock is determined at a beginning of the XO-mode. A second alignment of the first clock to the second clock is determined at the end of the XO-mode. An adjusted cycle count is determined by summating the fractional correction value with a summation of the first alignment and the second alignment divided by the first period.
    Type: Grant
    Filed: October 21, 2020
    Date of Patent: November 16, 2021
    Assignee: NXP B.V.
    Inventors: Jacek Tyminski, Wolfgang Kuchler, Georg Burgler, Sandeep Mallya, Pradeep Kumar Aithagani, Chinmay Gururaj Kathani
  • Patent number: 11177207
    Abstract: A transistor includes a semiconductor substrate having a first terminal and a second terminal. An interconnect structure is formed on an upper surface of the semiconductor substrate, the interconnect structure being formed of multiple layers of dielectric material and electrically conductive material. The electrically conductive material of the interconnect structure includes a pillar in electrical contact with the first terminal, a first runner electrically connected to the pillar, a tap interconnect in electrical contact with the second terminal, a second runner electrically connected to the tap interconnect, a shield structure positioned between the pillar and the tap interconnect, and a shield runner electrically connected to the shield structure, the shield runner overlying the second runner in a direction perpendicular to the upper surface of the semiconductor substrate.
    Type: Grant
    Filed: December 19, 2019
    Date of Patent: November 16, 2021
    Assignee: NXP USA, Inc.
    Inventors: Vikas Shilimkar, Kevin Kim, Charles John Lessard, Humayun Kabir
  • Patent number: 11175689
    Abstract: A communication system including a physical layer circuit, a timer circuit, and a turnaround controller. The physical layer circuit provides an early turnaround indication upon detection of a turnaround command and before completion of the turnaround command. The timer circuit is programmed with a timeout value indicative of a maximum time of a turnaround procedure initiated by the turnaround command. The turnaround controller starts the timer circuit in response to the early turnaround indication. A transmit controller may begin retrieving information to transmit from a memory in response to the early turnaround indication, and may begin transmitting the retrieved information if the turnaround procedure completes before timeout of the timer circuit. The retrieved information may be configuration information for a sensor. The turnaround controller provides an error indication if the timer circuit times out indicating a turnaround error. The error indication enables remedial action to be taken.
    Type: Grant
    Filed: March 17, 2020
    Date of Patent: November 16, 2021
    Assignee: NXP USA, Inc.
    Inventors: Maik Brett, Naveen Kumar Jain, Shreya Singh, Anshul Goel
  • Patent number: 11170093
    Abstract: A public key architecture (160) includes a dual certificate hierarchy which facilitates two independent authentication functions. One of the authentication functions authenticates an authentication device (164) to a verification device (166). The other authentication function authenticates a configuration device (162) to the authentication device (164). In some embodiments, the authentication process uses a lightweight certificate formed in conjunction with a lightweight signature scheme (370).
    Type: Grant
    Filed: July 25, 2018
    Date of Patent: November 9, 2021
    Assignee: NXP B.V.
    Inventor: Peter Maria Franciscus Rombouts
  • Patent number: 11171562
    Abstract: Multi-sense point voltage regulator systems are provided for usage in conjunction with power-regulated devices, such as system-on-chip and microcontroller unit devices. In embodiments, the multi-sense point voltage regulator system includes a multiplexer selector circuit and a voltage regulator. The multiplexer selector circuit is configured to: (i) monitor a local voltages at multiple sense points within an integrated circuit (IC) die circuit structure; and (ii) generate a feedback voltage indicative of a lowest one of the monitored local voltages. The voltage regulator is configured to generate a regulated power supply output voltage as a function of a differential between the feedback voltage and the reference voltage, with the regulated power supply output voltage provided to the IC die circuit structure to drive operation thereof.
    Type: Grant
    Filed: July 7, 2020
    Date of Patent: November 9, 2021
    Assignee: NXP USA, INC.
    Inventors: Andre Luis Vilas Boas, Marcelo Fukui, Andre Gunther
  • Patent number: 11170849
    Abstract: A memory includes a plurality of word line drivers with each driver controlling the voltage of a word line and the voltage of a select line during a memory operation. The driver operates to couple the select line to a first voltage setting terminal when the word line is asserted and couple the select line to a second voltage setting terminal when the word line is not asserted.
    Type: Grant
    Filed: September 17, 2020
    Date of Patent: November 9, 2021
    Assignee: NXP USA, INC.
    Inventors: Jon Scott Choy, Padmaraj Sanjeevarao, Jacob T. Williams
  • Patent number: 11169952
    Abstract: The disclosure relates to a data transmission interface for use in a first integrated circuit (IC) for encoding and sending a data packet from the first IC to a second IC via a data bus having four data wires, the data transmission interface arranged to generate four time-dependent binary signals which jointly encode the data packet in signal edges thereof, each of the signals being associated with a unique wire of the data bus and spanning a temporal cycle T within which are defined four consecutive time stamps T1 . . . T4 at which edges can occur in the signals, the data transmission interface further arranged to transmit the signals to the second IC substantially in parallel on their respective data wires, wherein: irrespective of the data packet content, at each time stamp T1 . . . T4 at least one of the four signals has an edge to enable clock recovery at the second IC.
    Type: Grant
    Filed: April 14, 2020
    Date of Patent: November 9, 2021
    Assignee: NXP B.V.
    Inventors: Jan-Peter Schat, Ling Wang, Michael Zimin
  • Patent number: 11172456
    Abstract: A communication system includes a digital data processor that produces a digital data sample and one or more control bits. A serialized transmit interface combines the digital data sample and the control bit(s) into one or more data packets and sends the data packet(s) over a signal line. A serialized receive interface receives the transmitted data packet(s) from the signal line and produces a reconstructed digital data sample and the control bit(s) from the transmitted data packet(s). A control circuit coupled to the serialized receive interface produces a control signal from the control bit(s). The communication system may include a converter circuit, which produces an RF input signal by performing a digital-to-analog conversion of the reconstructed digital data sample, and by upconverting the resulting analog data sample signal to RF. A power amplifier amplifies the RF input signal and modifies operation of a sub-circuit based on the control signal.
    Type: Grant
    Filed: November 3, 2020
    Date of Patent: November 9, 2021
    Assignee: NXP USA, Inc.
    Inventors: Nicholas Justin Mountford Spence, Yuhang Zhu, John Vaglica
  • Patent number: 11171793
    Abstract: A method and data processing system is provided for detecting an attack on a physically unclonable function (PUF). In the method, a first list of PUF responses to challenges is produced during production testing of an integrated circuit comprising the PUF. The first list is stored in a memory on the integrated circuit. A second list of PUF responses to the challenges is produced during normal operation of the integrated circuit in the field. The second list is compared to the first list. A difference between entries of the first and second lists computed. If the difference is greater than a threshold difference, then an indication of a hardware trojan is generated. The method may also include monitoring a series of challenges for an indication of a non-random pattern in the series. Detection of a non-random pattern may indicate a modeling attack.
    Type: Grant
    Filed: October 1, 2019
    Date of Patent: November 9, 2021
    Assignee: NXP B.V.
    Inventor: Jan-Peter Schat
  • Patent number: 11171676
    Abstract: Disclosed is a method for sensitivity control in a near-field communication, NFC, device operating in a receiving mode. The method comprises calculating a threshold value, using a threshold value calculating unit, as a function of a determined current received signal strength indicator, RSSI, value, optionally a determined current gain control, GC, value, and further optionally a so-called margin value that is a product-specific parameter, and applying the calculated threshold value as a threshold parameter to a threshold comparison unit, which is configured to receive, as input.
    Type: Grant
    Filed: July 14, 2020
    Date of Patent: November 9, 2021
    Assignee: NXP B.V.
    Inventors: Ulrich Andreas Muehlmann, Shuli Chi, Martin Hrastnik
  • Patent number: 11172512
    Abstract: A communication device receives a trigger frame that is configured to: trigger a contention-based uplink orthogonal frequency multiple access (OFDMA) transmission by multiple communication devices, and indicate a predetermined length of the contention-based uplink OFDMA transmission, wherein the predetermined length corresponds to contention-based uplink OFDMA transmissions. Responsive to receiving the trigger frame, the communication device generates a data unit having the predetermined length, and responsive to receiving the trigger frame, transmits the data unit as part of a contention-based uplink OFDMA transmission.
    Type: Grant
    Filed: November 4, 2019
    Date of Patent: November 9, 2021
    Assignee: NXP USA, INC.
    Inventors: Yakun Sun, Hongyuan Zhang
  • Patent number: 11170109
    Abstract: An SoC device has a boot-code memory that stores boot code and a boot core that accesses the boot-code memory to execute the boot code at startup. The boot core is capable of executing application code after the startup is complete. One or more master cores execute application code. An access control circuit prevents the boot core from accessing the boot-code memory when application code is being executed.
    Type: Grant
    Filed: April 16, 2019
    Date of Patent: November 9, 2021
    Assignee: NXP USA, INC.
    Inventors: Rohit Kumar Sinha, Arun Jain, Himanshu Shekhar Thakur, Neha Agarwal
  • Patent number: 11171077
    Abstract: A semiconductor device is assembled using a lead frame having leads that surround a central opening. The leads have proximal ends near to the central opening and distal ends spaced from the central opening. A heat sink is attached to a bottom surface of the leads and a semiconductor die is attached to a top surface of the leads, where the die is supported on the proximal ends of the leads and spans the central opening. Bond wires electrically connect electrodes on an active surface of the die and the leads. An encapsulant covers the bond wires and at least the top surface of the leads and the die. The distal ends of the leads are exposed to allow external electrical communication with the die.
    Type: Grant
    Filed: June 22, 2020
    Date of Patent: November 9, 2021
    Assignee: NXP USA, INC.
    Inventors: You Ge, Meng Kong Lye, Zhijie Wang
  • Patent number: 11171696
    Abstract: Various embodiments relate to a method for processing received distributed multiple-input and multiple-output (DMIMO) OFDM signals from a plurality of transmitters, including: performing an initial carrier frequency offset (CFO) correction; receiving a plurality of OFDM symbols; re-constructing the channel every N symbols based upon a channel estimate for each transmitter and an estimate of residual CFO for each of the transmitters based upon the long term fields (LTF), wherein N is an integer; and equalizing the received OFDM symbols using the re-constructed channel.
    Type: Grant
    Filed: July 30, 2020
    Date of Patent: November 9, 2021
    Assignee: NXP USA, Inc.
    Inventors: Hari Ram Balakrishnan, Sri Varsha Rottela, Ankit Sethi, Vijay Ahirwar, Nilesh Nilkanth Khude, Sudhir Srinivasa
  • Patent number: 11171687
    Abstract: Embodiments of methods and systems for operating a communications device that communicates via inductive coupling are described. In an embodiment, a method for operating a communications device that communicates via inductive coupling involves detecting a falling signal edge corresponding to a received signal at the communications device based on a falling signal edge threshold, detecting a rising signal edge corresponding to the received signal based on a rising signal edge threshold, where the rising signal edge threshold is independent from the falling signal edge threshold, and decoding the received signal based on the detected falling signal edge and the detected rising signal edge. Other embodiments are also described.
    Type: Grant
    Filed: November 22, 2019
    Date of Patent: November 9, 2021
    Assignee: NXP B.V.
    Inventors: Steve Charpentier, Ulrich Andreas Muehlmann, Stefan Mendel