Patents Assigned to NXP
  • Patent number: 11204832
    Abstract: A method is provided for detecting a cold boot attack in a data processing system. The data processing system includes a processor, a memory with ECC, and a monitor circuit. In the method, during a boot process of the data processing system, the monitor circuit counts read and write accesses to the memory and maintains a count of the number of errors in the memory detected by the ECC. The read and write access count and the error count are used to detect suspicious activity that may indicate a cold boot attack on the memory. A data processing system that implements the method is also provided.
    Type: Grant
    Filed: April 2, 2020
    Date of Patent: December 21, 2021
    Assignee: NXP B.V.
    Inventor: Jan-Peter Schat
  • Patent number: 11204987
    Abstract: A method is provided for generating a test for distinguishing humans from computers. The computer may include a machine learning model. A reference sample in a first category is selected. A first plurality of samples is selected from the first category. The samples may be images. Adversarial examples are created for one or more of the first plurality of samples. Each of the adversarial examples are created for one or more other categories different from the first category. A second plurality of samples is selected from the one or more other categories different from the first category. An adversarial example is created from one or more of the second plurality of samples for the first category. The reference sample and first and second pluralities of samples as modified to be adversarial examples, are presented for testing by a user to determine if the user is a human or a computer.
    Type: Grant
    Filed: November 7, 2019
    Date of Patent: December 21, 2021
    Assignee: NXP B.V.
    Inventor: Nikita Veshchikov
  • Patent number: 11204410
    Abstract: Aspects of the present disclosure are directed to a method and/or apparatus involving frequency modulated continuous wave (FMCW) radar signals. As my be implemented in accordance with one or more embodiments, receiver circuitry is configured and arranged to receive a FMCW radar signal having an information signal embedded into a radar waveform, and to indicate a relationship in the FMCW radar signal between beat frequency magnitude and time delay. A filter processing circuit is configured and arranged to filter the information signal in the FMCW radar signal by applying a group delay function based on the relationship between beat frequency magnitude and time delay. Signal processing circuitry is configured and arranged to detect a remote object by using the filtered FMCW radar signal.
    Type: Grant
    Filed: February 11, 2019
    Date of Patent: December 21, 2021
    Assignee: NXP B.V.
    Inventors: Feike Guus Jansen, Francesco Laghezza, Franz Lampel
  • Patent number: 11201508
    Abstract: A power-transmitter-unit comprises a power-transmitting-coil and a resonant-capacitor that define an LC circuit. A controller defines a power-transmission-mode of operation and a foreign-object-detection-mode of operation. In the power-transmission-mode of operation: a power-stage provides a potential-difference across a first-end and a second-end of the LC circuit. In the foreign-object-detection-mode of operation: for a recuperation-time-interval, the power-stage provides a potential-difference across the first-end and the second-end of the LC circuit that has the opposite polarity to the current through the power-transmitting-coil; after expiry of the recuperation-time-interval, the first-end of the LC circuit is connected to the second-end of the LC circuit such that the LC circuit is short-circuited and defines a closed-LC-circuit; and the controller receives measured-signalling that is representative of an operating parameter of the power-transmitter-unit.
    Type: Grant
    Filed: March 7, 2019
    Date of Patent: December 14, 2021
    Assignee: NXP USA, Inc.
    Inventors: Zbynek Mynar, Jozef Cicka, Vojtéch Musil
  • Patent number: 11200098
    Abstract: A technique for operating a system including a plurality of processors and a shared resource includes executing a first instruction by a first processor of the plurality of processors. The first instruction generates a reservation of the shared resource for the first processor. The technique includes, after generating the reservation of the shared resource for the first processor, executing a spin lock by the first processor until successful execution of a second instruction acquires a lock of the shared resource. The technique includes disabling interrupts of the first processor in response to an indicator of the successful execution of the second instruction. The first instruction may be a load and reserve instruction and the second instruction may be a conditional store instruction.
    Type: Grant
    Filed: February 19, 2019
    Date of Patent: December 14, 2021
    Assignee: NXP USA, Inc.
    Inventors: Sourav Roy, Sneha Mishra
  • Patent number: 11202310
    Abstract: A communication device determines, in connection with a prior uplink multi-user (UL MU) communication in which the communication device participated, whether the communication device is to use one or more first channel access parameters, or one or more second channel access parameters for accessing a communication medium for a single user (SU) transmission by the communication device, where using the one or more first channel access parameters is associated with a greater probability of obtaining access to the communication medium as compared to using the one or more second channel access parameters. Depending on the determination made, the communication device uses the one or more first channel access parameters, or the one or more second channel access parameters to attempt to access the communication medium. In response to accessing the communication medium, the communication device transmits the SU transmission via the communication medium.
    Type: Grant
    Filed: February 17, 2020
    Date of Patent: December 14, 2021
    Assignee: NXP USA, INC.
    Inventors: Jinjing Jiang, Liwen Chu, Lei Wang, Yakun Sun, Hongyuan Zhang, Huiling Lou
  • Patent number: 11200170
    Abstract: A data processing system includes a processor, a memory, and a cache. The cache includes a cache array, cache control circuitry coupled to receive an access address corresponding to a read access request from the processor and configured to determine whether the received access address hits or misses in the cache array, pre-load control storage circuitry outside the cache array and configured to store a pre-load cache line address and a corresponding stride value, and pre-load control circuitry coupled to the cache control circuit rand the pre-load control storage circuitry. The pre-load control circuitry is configured to receive the access address corresponding to the read access request from the processor and selectively initiating a pre-load from the memory to the cache based on whether a cache line address portion of the access address matches the stored pre-load cache line address.
    Type: Grant
    Filed: December 4, 2019
    Date of Patent: December 14, 2021
    Assignee: NXP USA, Inc.
    Inventors: Paul Kimelman, Brian Christopher Kahne
  • Patent number: 11201605
    Abstract: A buffer stage for amplifying a clock signal generated by a current controlled oscillator that receives a first current at a first supply voltage from a first current source. The buffer stage comprises an input terminal configured to receive the clock signal; an output terminal configured to output a buffered signal; at least one buffer, coupled between the input and output terminal, configured to receive a second current at a second supply voltage and buffer the clock signal to generate the buffered signal; a clamping circuit that receives the first current and the second current, and generates a first supply voltage and a second supply voltage. The clamping circuit clamps the second supply voltage equal to the first supply voltage.
    Type: Grant
    Filed: December 17, 2020
    Date of Patent: December 14, 2021
    Assignee: NXP USA, Inc.
    Inventors: Jianzhou Wu, Jiawei Fu, Yang Wang, Bin Zhang
  • Patent number: 11199621
    Abstract: In accordance with a first aspect of the present disclosure, a transponder is provided, comprising: a frequency detector configured to monitor an output frequency of a clock-stop sensor of said transponder, wherein said frequency detector is further configured to determine if said output frequency falls within a response detection frequency range of an external reader, and a frequency shifter configured to shift, in response to the frequency detector determining that the output frequency falls within said response detection frequency range, said output frequency to a value outside said response detection frequency range. In accordance with a second aspect of the present disclosure, a corresponding method of operating a transponder is conceived. In accordance with a third aspect of the present disclosure, a corresponding computer program is provided.
    Type: Grant
    Filed: February 15, 2019
    Date of Patent: December 14, 2021
    Assignee: NXP B.V.
    Inventors: Shankar Joshi, Raghavendra Kongari, Björn Rasmussen
  • Patent number: 11201502
    Abstract: A respective first signal is applied to a first terminal of each of one or more litz coils and each of one or more printed circuit board (PCB) coils. A respective second signal is received from a second terminal associated with each of the one or more litz coils and the one or more PCB coils. The respective second signal is based on the respective first signal applied to the first terminal of each of one or more litz coils and each of one or more PCB coils. A coil is selected from the one or more litz coils and the one or more PCB coils where the selected coil is based on the respective second signal from the second terminal associated with each of the one or more litz coils and the one or more PCB coils to wirelessly transfer the power to an electronic device.
    Type: Grant
    Filed: June 16, 2020
    Date of Patent: December 14, 2021
    Assignee: NXP USA, Inc.
    Inventors: Jaehee Park, Ivan Sieklik
  • Patent number: 11201113
    Abstract: An integrated circuit comprising a semiconductor substrate and a passive coupler located on the substrate. The coupler includes a solenoid. The coupler also includes a signal line passing through the solenoid. A method of making an integrated circuit. The method includes providing a semiconductor substrate and forming a passive coupler in a metallization stack on the substrate. Forming the passive coupler in the metallization stack on the substrate includes forming one or more windings of the solenoid using patterned metal features in a plurality of metal layers of the metallization stack. Forming the passive coupler in the metallization stack on the substrate also includes forming a signal line using one or more patterned metal features in one or more metal layers of the metallization stack. The signal line passes through the solenoid.
    Type: Grant
    Filed: July 26, 2019
    Date of Patent: December 14, 2021
    Assignee: NXP B.V.
    Inventor: Olivier Tesson
  • Patent number: 11200128
    Abstract: Embodiments of a device and method are disclosed. In an embodiment, a network interface device is disclosed. The device includes a network interface configured to provide an interface to a network, a functional component interface configured to provide an interface to a functional component, and distributed test logic located in a path between the network interface and the functional component interface and configured to manage test information related to testing of the functional component and to communicate test information between the network interface and the distributed test logic and between the functional component interface and the distributed test logic.
    Type: Grant
    Filed: August 28, 2018
    Date of Patent: December 14, 2021
    Assignee: NXP B.V.
    Inventors: Abhijit Kumar Deb, Hubertus Gerardus Hendrikus Vermeulen, Lucas Pieter Lodewijk van Dijk
  • Publication number: 20210385573
    Abstract: A method, system, apparatus, and architecture are provided for generating a sound-enhanced sensing envelope by using a plurality of sensors and one or more passive sound sensors of a vehicle to collect and process sensor data signals characterizing an exterior environment of the vehicle, thereby generating a sensing envelope around the vehicle using direct sensing data signals and a sound-enhanced sensing envelope around the vehicle using indirect sensing data signals which is used to evaluate advanced driver assistance system commands for the vehicle with respect to safety-related events identified by the indirect sensing data signals.
    Type: Application
    Filed: August 5, 2020
    Publication date: December 9, 2021
    Applicant: NXP USA, Inc.
    Inventors: Daniel Dumitru Popa, Canstantin Razvan Chivu, Marius Lucian Andrei
  • Patent number: 11194018
    Abstract: A radar sensor for use in a vehicle is described. The radar sensor comprising: at least one transmitter and at least once receiver to transmit and receive radar signals of the radar sensor; an acceleration sensor to measure the acceleration of said radar sensor or the chassis of said vehicle; a processor coupled to said acceleration sensor to calculate a tilt in a radar signal projected from said vehicle using said measured acceleration; a memory for storing said calculated radar tilt.
    Type: Grant
    Filed: April 16, 2019
    Date of Patent: December 7, 2021
    Assignee: NXP USA, Inc.
    Inventor: Ernst Seler
  • Patent number: 11196391
    Abstract: Embodiments of a temperature compensation circuit and a temperature compensated amplifier circuit are disclosed. In an embodiment, a temperature compensation circuit includes a bias reference circuit having serially connected transistor devices and a driver transistor device connected to the bias reference circuit. At least one of the serially connected transistor devices includes a resistor connected between two terminals of the at least one of the serially connected transistor devices. The driver transistor device is configured to generate a drive current based on a resistance value of the resistor.
    Type: Grant
    Filed: July 31, 2019
    Date of Patent: December 7, 2021
    Assignee: NXP USA, Inc.
    Inventors: Joseph Staudinger, Yu You, Donald Vernon Hayes
  • Patent number: 11196411
    Abstract: A circuit including a device including a first and second node. The device operating in at least an enabled mode and a disabled mode. The circuit including a voltage control circuit. The voltage control circuit including a current source for sourcing current to or sinking current from the first node during the disabled mode and a voltage difference detector including an output for providing an indication of a measured voltage difference between the first node and the second node. The voltage control circuit includes a current source control circuit including a first input to receive the indication of the measured voltage difference and an output to control current sourced to or sinked from the first node by the current source to limit a voltage difference between the first and second node based on a comparison between the indication of the measured voltage difference and an indication of a target voltage difference.
    Type: Grant
    Filed: February 7, 2019
    Date of Patent: December 7, 2021
    Assignee: NXP USA, Inc.
    Inventors: Srikanth Jagannathan, Kumar Abhishek
  • Patent number: 11196429
    Abstract: Locking time for a phase-locked loop is decreased by selectively controlling a division value of the feedback divider during the first division cycle to reduce the initial phase error. The division value of the feedback divider during the first division cycle is selectively set such that the locking phase relationship between the two phase detector input signals is achieved at the end of the first division cycle.
    Type: Grant
    Filed: July 27, 2020
    Date of Patent: December 7, 2021
    Assignee: NXP USA, Inc.
    Inventors: Stefano Dal Toso, Mathieu Perin
  • Patent number: 11196390
    Abstract: Power amplifier devices and methods for fabricating power amplifier devices containing frontside heat extraction structures are disclosed. In embodiments, the power amplifier device includes a substrate, a radio frequency (RF) power die bonded to a die support surface of the substrate, and a frontside heat extraction structure further attached to the die support surface. The frontside heat extraction structure includes, in turn, a transistor-overlay portion in direct thermal contact with a frontside of the RF power die, a first heatsink coupling portion thermally coupled to a heatsink region of the substrate, and a primary heat extraction path extending from the transistor-overlay portion to the first heatsink coupling portion. The primary heat extraction path promotes conductive heat transfer from the RF power die to the heatsink region and reduce local temperatures within a transistor channel of the RF power die during operation of the power amplifier device.
    Type: Grant
    Filed: April 23, 2020
    Date of Patent: December 7, 2021
    Assignee: NXP USA, Inc.
    Inventors: Edward Christian Mares, Lakshminarayan Viswanathan, David James Dougherty
  • Patent number: 11194379
    Abstract: A wake-up circuit and method are provided for detecting and preventing false positive wake-up events in an electronic device in a sleep mode. Methodology entails producing first, second, and third sensor signals at successive first, second, and third instants in time in response to a physical stimulus detected by a sensor of the wake-up circuit. The first sensor signal is selected to be a reference value. A first difference value is determined between the second sensor signal land the reference value, a second difference value is determined between the third sensor signal and the reference value, and communication of a wake-up signal to the electronic device is prevented when at least one of the first and second difference values fails to exceed a threshold value.
    Type: Grant
    Filed: March 30, 2020
    Date of Patent: December 7, 2021
    Assignee: NXP USA, Inc.
    Inventors: Volker Dietmar Wahl, Philippe Bernard Roland Lance, Jacques Trichet
  • Patent number: 11194357
    Abstract: Embodiments of a method and a device are disclosed. In an embodiment, a method for operating a bias controller for an amplifier circuit involves obtaining temperature data corresponding to a temperature of the amplifier circuit, generating a proportional to absolute temperature (PTAT) bias voltage based on a first PTAT slope when the temperature is within a first range of temperatures or a second PTAT slope when the temperature is within a second range of temperatures, wherein the second PTAT slope is greater than the first PTAT slope, and biasing the amplifier circuit based on the generated PTAT bias voltage.
    Type: Grant
    Filed: September 13, 2019
    Date of Patent: December 7, 2021
    Assignee: NXP USA, Inc.
    Inventors: Elie A. Maalouf, Xu Jason Ma, Ngai-Ming Lau