Abstract: A circulator-coupler device includes a ferrite element, a resonator over and aligned along an axis with the ferrite element, and a plurality of resonator ports connected to the resonator. The plurality of resonator ports includes first and second resonator ports, and a first portion of a perimeter of the resonator extends between the first and second resonator ports. The circulator further includes a coupler element positioned across a gap from the first portion of the perimeter of the resonator, and a coupler port connected to the coupler element. The device also may include a permanent magnet aligned along the axis with the ferrite element, where the permanent magnet biases the ferrite element and causes a signal conducted through the resonator to have a directionality along a rotational direction that extends from the first resonator port to the second resonator port.

Abstract: As may be used in connection with frequency-modulated (FM) radio systems and receivers processing FM broadcast transmissions, exemplary aspects are directed to a method may be performed by the receiver circuitry to receive FM broadcast signaling within a particular bandwidth for which a plurality of target channels are to have a specified channel spacing. The method may include: assessing detected energy for a first adjacent channel having the specified channel spacing and having a frequency immediately adjacent to a targeted one of the plurality of target channels; and discerning whether the detected energy is associated with ultra-sonic energy in detected modulation energy (e.g., ultra-sonic noise in an MPX signal), and/or is associated with modulation energy (e.g., due to over-modulation) from a second adjacent channel also having such specified channel spacing.

Abstract: A method of manufacturing a hybrid package including a flat package and a Wafer Level Chip Scale Package (WLCSP) is disclosed. The method includes fabricating a strip including a plurality of flat packages attached to each other via metal pins, turning the strip upside down, applying a layer of a thermal interface material (TIM) on each of the flat packages while the each of the flat packages is turned upside down, mounting the WLCSP on the layer of the TIM such that a top side of the WLCSP is interfaced with the layer of the TIM, curing the layer of the TIM and singulating each of the flat packages by cutting the metal pins and bending the metal pins.

Abstract: A power amplifier includes a semiconductor die, and an amplifier and bias circuit integrally formed with the semiconductor die. The die has opposed first and second sides, and a device bisection line extends between the first and second sides. The bias circuit includes a multi-point input terminal with first and second terminals that are electrically connected through a conductive path that extends across the device bisection line, and one or more bias circuit components connected between the multi-point input terminal and the amplifier. The amplifier may include a field effect transistor (FET) with gate and drain terminals, and the bias circuit component(s) are electrically connected between the multi-point input terminal and the gate terminal. In addition or alternatively, the bias circuit component(s) are electrically connected between a multi-point input terminal and the drain terminal. The one or more components may include a resistor-divider circuit.

Abstract: A differential bus network comprising: a bus comprising two bus wires; at least three nodes each comprising: a transceiver comprising: bus terminals for coupling, respectively, to the two wires of the bus; a receiver arrangement configured to receive differential signalling from the bus terminals and determine a digital receive signal based on said differential signalling; and a transmitter arrangement configured to apply differential signalling to the bus terminals based on a digital transmit signal, the transmitter arrangement comprising a first transmitter configured to increase the potential difference between the wires of the bus to a first differential voltage state and maintain the first differential state and a suppression element configured to decrease the potential difference between the two wires of the bus towards a second differential voltage state, the transmitter arrangement further comprising a resistor coupled between the bus terminals configured to at least maintain the second differential v

Abstract: Embodiments of a method and a device are disclosed. In an embodiment, a method for operating a radar system is disclosed. The method involves generating a chirp signal having a repeating pattern of chirps, each chirp in the repeating pattern of chirps having a base frequency and a chirp bandwidth, wherein the repeating pattern of chirps includes at least two chirps that differ from each other in at least one of base frequency and chirp bandwidth, transmitting a radar signal according to the chirp signal, receiving radio frequency energy that includes a reflected portion of the radar signal, and selecting for processing from the received radio frequency energy a signal that matches the repeating pattern of chirps of the chirp signal.

Abstract: Embodiments described herein provides a system for detecting data received in a low power low rate (LPLR) data frame format. A mixed mode LPLR frame may be falsely detected by an 802.11n device as an 802.11n packet. When the false detection occurs, the PHY-CAA indication may be erroneously set, which leads to a communication error. To prevent the false detection by an 802.11n device, embodiments described herein describes adding a redundant “dummy” 4 ?s orthogonal frequency division multiplexing (OFDM) symbol with binary phase-shift keying (BPSK) modulation before the LPLR preamble in the LPLR frame, to differentiate from data symbols in an 802.11n packet.

Abstract: Doherty power amplifier (PA) devices (e.g., packages and modules) including integrated output combining networks are disclosed. In embodiments, the Doherty PA device includes a first amplifier die having a first transistor with a first output terminal at which a first amplified signal is generated, a second amplifier die having a second transistor with a second output terminal at which a second amplified signal is generated, and an output combining network. The output combining network includes, in turn, a combining node integrally formed with the second amplifier die and electrically coupled to the second output terminal. At least one die-to-die bond wire electrically couples the first output terminal to the combining node. The at least one die-to-die bond wire has an electrical length, which is results in a 90 degree phase shift imparted to the first amplified signal between the first output terminal and the combining node.

Abstract: A method and circuit for a data processing system provide a hardware accelerator repeat control instruction (402A) which is executed with a hardware accelerator instruction (402B) to extract and latch repeat parameters from the hardware accelerator repeat control instruction, such as a repeat count value (RPT_CNT), a source address offset value (ADDR_INCR0), and a destination address offset value (ADDR_INCR1), and to generate a command to the hardware accelerator (205) to execute the hardware accelerator instruction a specified plurality of times based on instruction parameters from the hardware accelerator instruction by using the repeat count value to track how many times the hardware accelerator instruction is executed and by automatically generating, at each execution of the hardware accelerator instruction, additional source and destination addresses for the hardware accelerator from the repeat parameters until the hardware accelerator instruction has been executed the specified plurality of times by the

Abstract: A MIPI CSI-2/D-PHY receiving device is configured to handle being hot plugged to MIPI CSI-2/D-PHY transmitting device. During a hot plugging event, the MIPI CSI-2/D-PHY receiving device has not been initialized by receipt from the MIPI CSI-2/D-PHY transmitting device of a Stop State signal of duration TINIT. Though the MIPI CSI-2/D-PHY transmitting device is already transmitting data associated with a partial frame, the MIPI CSI-2/D-PHY receiving device will not enter into an error or unknown state, and will ignore line start/end and frame end events and drop the data packets associated with the partial frame until a frame start event corresponding to a full frame is received from the MIPI CSI-2/D-PHY transmitting device.

Abstract: In an 802.11be wireless system, data units are generated for transmission by configuring a transmitting device to process encoding parameters, including a first encoding parameter NSD and a second encoding parameter NSD,short, to select a padding boundary from pre-defined padding boundaries in the last symbol that will most closely include the number of information bits NEXCESS in the last symbol and to append padding bits to the number of information bits NEXCESS to fill up to the selected padding boundary in the last symbol, thereby generating pre-encoded data bits which are encoded for data transmission, where at least the first encoding parameter NSD is specified for an aggregated resource unit size that is allowed under the 802.11be protocol as a sum of NSD values for at two other resource units.

Abstract: Channel availability information associated with data traffic between a Master and a Slave within an interconnection network (“ICN”) in a System-on-Chip (“SoC”) is monitored by a channel performance monitor in order to improve the performance of the ICN. The channel availability information is fed back to certain Masters to control their data traffic into the ICN. The channel performance monitor monitors and evaluates the data traffic handled by switches within the ICN that can potentially interfere with communication paths between particular Masters and Slaves, and control the initiation of data traffic from predetermined Masters.

Abstract: Embodiments of a device and method are disclosed. In an embodiment, a method of communications involves allocating communications devices of a wired communications network to clusters, assigning addresses to the clusters, where each communications device within one of the clusters has an identical address, and conducting communications between the communications devices based on the addresses assigned to the clusters.

Abstract: Embodiments of a system and method are disclosed. In an embodiment, a LiDAR (Light Detection and Ranging) system that can include a sensor circuit comprising a controller unit, a transmitter, a gating circuit, and a receiver element, wherein the gating circuit is connected to the controller unit and to the receiver element, wherein signals detected by the sensor circuit correspond to at least one physical object located in an operating region with respect to a location of the sensor circuit and based on multiple measurements. The gating circuit can range-gate the receiver element based on a range-gating waveform, and the controller unit can provide a phase-delay parameter for phase shifting the range-gating waveform with different phase values relative to a light signal transmitted by the transmitter for different measurements by the sensor circuit.

Abstract: A radar and/or camera system may include a receiver subsystem that receives image and/or radar data from one or more imaging/radar subsystems via multiple data lanes. A vision processor of the system may receive a data stream that includes the image and/or radar data and one or more synchronization signals including a vertical sync signal. The receiver subsystem may include a timing event generator that toggles the vertical sync signal in response to detecting certain timing event errors in order to correct these timing event errors without interrupting normal operation of the system. The receiver subsystem may include sync monitoring circuitry that may detect synchronization errors that occur when synchronization signal pulses received by the receiver subsystem do not match a predefined synchronization pattern within a scan window of predefined length. The system may be reset in response to detection of such synchronization errors.

Abstract: A system includes a video generation circuit (102) to generate first graphics information, a display circuit (112) to display the graphics information, and a low voltage differential signaling (LVDS) (120) video interface to couple graphics information from the video generation circuit to the display circuit. The display circuit can determine that a first channel (204) of the LVDS video interface is corrupted. In response, the display circuit provides a remediation signal (205) to direct the video generation circuit (102) to operate in an alternative operating mode (208).

Abstract: A system-on-chip (SoC) is disclosed. The SoC includes a set of fake fault injection circuits and a critical intellectual property (IP) core that includes first and second control circuits. The first and second control circuits are each operable in a test mode and a functional mode. The first and second control circuits are operated in the functional mode in lockstep in an absence of a fake fault input. In a presence of the fake fault input, one of the first and second control circuits is switched from the functional mode to the test mode. One of the first and second control circuits operating the test mode generates a fake fault response for the fake fault input. The critical IP core is determined as one of error-free and erroneous based on a detection of the generated fake fault response as one of error-free and erroneous, respectively.

Abstract: A system-on-chip (SoC) includes a processor, a built-in self-testing (BIST) circuitry, and an adaptive masking circuitry. The processor generates a sweep enable (SWEN) signal to initiate a self-testing operation of the SoC. The BIST circuitry receives the SWEN signal and generates a set of sweep events, such that a transition of the processor from a low power (LP) mode to an active mode is initiated based on the generation of each sweep event. The BIST circuitry further receives a status signal, and identifies a subset of sweep events at which the transition of the processor from the LP mode to the active mode failed, for generating sweep failure data. The adaptive masking circuitry receives the sweep failure data and generates a mask signal, to prevent a transition of the first processor from the LP mode to the active mode, during a non-testing operation of the SoC.

Abstract: A system and method of power mode management for a processor providing safe and robust transitioning between normal and low power modes to meet low current requirements and to ensure accurate power mode transition communications. A two step process includes receiving a digital code, starting a standby entry timer, and receiving a low power request indication before timeout of the standby entry timer to ensure a valid request, and otherwise resetting upon timer timeout. A watchdog timer ensures that a maximum standby duration is not exceeded. An acknowledge timer ensures valid communication between modules of a power management IC. Memory elements ensure and maintain valid states of reset and safe state pins during standby. Self tests are performed in which test failure prevents transition to the low power mode. A power good indication ensures the processor that the supply voltages are suitable for both low power and normal operation.

Abstract: A circuit is provide comprising a first input coupled to a transmit data input of a bus transceiver; and a first output coupled to a bus. The circuit is configured to be coupled in parallel with the bus transceiver. The circuit is further configured to, in response to a dominant to recessive transition on the transmit data input, lower an impedance of the bus.