Abstract: A method of routing electrical connections in a wafer-on-wafer structure comprises, bonding a metal bonding pad of a first wafer to a metal bonding pad of a second wafer; bonding first wafer to the second wafer with a material different from the metal bonding pads; forming metal interconnect structures connecting the metal bonding pad of the first wafer to a first device disposed within a first and second side of the first wafer; and forming metal interconnect structures connecting the metal bonding pad of the second wafer to a second and third devices disposed within the second wafer, to connect the first device to the second and third devices through the metal bonding pads, wherein the electrical connections of the devices between the first and second wafers do not have a through-via that passes completely through the first or the second wafer.

Abstract: A pixel cell includes a first photodiode, a second photodiode, a first deep trench isolation region, a second deep trench isolation region, a buffer oxide layer, and a light attenuation layer. The attenuation layer partially encapsulates the first photodiode by extending laterally from the first deep trench isolation region to the second deep trench isolation region between the semiconductor material and the buffer oxide layer.

Abstract: A system comprising a polarization CMOS image sensor, at least one processor and a non-transitory computer-readable medium having computer-executable instructions stored thereon that, in response to execution by the at least one processor, cause the system to perform actions including receiving, from the polarization CMOS image sensor, polarization information and two-dimensional image information. The polarization information is processed using a machine learning model to generate an output that indicates whether the polarization information represents a valid biometric measurement of a physical feature of a subject.

Abstract: A photomultiplier pixel cell includes a photon detector coupled to detect an incident photon. A quenching circuit is coupled to quench an avalanche current in the photon detector. An enable circuit is coupled to the photon detector to enable and disable the photon detector in response to an enable signal. A buffer circuit is coupled to the photon detector to generate a digital output signal having a pulse width interval in response to the avalanche current triggered in the photon detector. A first one of a plurality of inputs of a digital-to-analog converter is coupled to the buffer circuit to receive a digital output signal. The digital-to-analog converter is coupled to generate an analog output signal having a magnitude that is responsive to a total number of digital output signals received concurrently within the pulse width interval at each one of the plurality of inputs of the digital-to-analog converter.

Abstract: An image sensor includes a substrate material. The substrate material includes a plurality of photodiodes disposed therein. The plurality of photodiodes includes a plurality of small photodiodes (SPDs) and a plurality of large photodiodes (LPDs) larger than the SPDs. An array of color filters is disposed over the substrate material. A buffer layer is disposed between the substrate material and the array of color filters. A metal pattern is disposed between the color filters in the array of color filters, and between the array of color filters and the buffer layer. An attenuation layer is disposed between the substrate material and the array of color filters. The attenuation layer is above and aligned with the plurality of SPDs and a portion of each of the plurality of LPDs. An edge of the attenuation layer is over one of the plurality of LPDs.

Abstract: An image sensing device includes an image sensing circuit, a voltage supply grid, bitlines, and a control circuit. The image sensing circuit includes pixels arranged in rows and columns. Each one of the bitlines is coupled to a corresponding one of the columns. The voltage supply grid is coupled to the pixels. The control circuit is coupled to output at least a row select signal and a transfer signal to the rows. Each one of the rows is selectively coupled to the bitlines to selectively output image data signals in response to the row select signal and the transfer signal. Each one of the rows is further selectively coupled to the bitlines to selectively clamp the bitlines in response to the row select signal and the transfer signal. Each one of the rows is selectively decoupled from the bitlines in response to the row select signal.

Abstract: An image sensor package includes a transparent substrate with a recess formed in the transparent substrate, and an image sensor positioned in the recess so that light incident on the transparent substrate passes through the transparent substrate to the image sensor. The image sensor package also includes a circuit board electrically disposed in the recess and coupled to receive image data from the image sensor, and the image sensor is positioned in the recess between the circuit board and the transparent substrate.

Abstract: A sensor includes a photodiode disposed in a semiconductor material to receive light and convert the light into charge, and a first floating diffusion coupled to the photodiode to receive the charge. A second floating diffusion is coupled to the photodiode to receive the charge, and a first transfer transistor is coupled to transfer the charge from the photodiode into the first floating diffusion. A second transfer transistor is coupled to transfer the charge from the photodiode into the second floating diffusion, and an inductor is coupled between a first gate terminal of the first transfer transistor and a second gate terminal of the second transfer transistor. The inductor, the first gate terminal, and the second gate terminal form a resonant circuit.

Abstract: A switch driver circuit includes a first transistor coupled between a voltage supply and a first output node. A second transistor is coupled between the first output node and a first discharge node. A first slope control circuit is coupled to the first discharge node to discharge the first discharge node at a first slope. A third transistor is coupled between the voltage supply and a second output node. A fourth transistor is coupled between the second output node and a second discharge node. A second slope control circuit coupled to the second discharge node to discharge the second discharge node at a second slope. The first and second slopes are mismatched.

Abstract: A pixel cell includes a first subpixel and a plurality of second subpixels. Each subpixel includes a photodiode to photogenerate image charge in response to incident light. Image charge is transferred from the first subpixel to a floating diffusion through a first transfer transistor. Image charge is transferred from the plurality of second subpixels to the floating diffusion through a plurality of second transfer transistors. An attenuation layer is disposed over the first subpixel. The first subpixel receives the incident light through the attenuation layer. The plurality of second subpixels receive the incident light without passing through the attenuation layer. A dual floating diffusion (DFD) transistor is coupled to the floating diffusion. A capacitor is coupled to the DFD transistor.

Abstract: An image sensor includes a pixel array with active rows of pixel cells, a black level calibration row with black image data generation circuits coupled to generate black image data signals representative of an absence of the incident light, and a dummy row with black level clamping circuits coupled to receive a black sun reference voltage to clamp bitlines of the pixel array, and a black level calibration circuit coupled to receive the black sun reference voltage to generate a black sun calibration voltage. A black sun feedback circuit is coupled to generate the black sun reference voltage in response to the black sun calibration voltage and a black level sample reference, and a black level sampling circuit is coupled to the bitlines to sample the black image data signals to generate the black level sample reference received by the black sun feedback circuit.

Abstract: A data transmission circuit of an image sensor. In one embodiment, the data transmission circuit includes a plurality of banks coupled in a series. A peripheral bank of the plurality of transmission banks is coupled to a function logic. Each bank includes a plurality of local buffers coupled to a local buffer control and a plurality of global buffers coupled to a global buffer control. The local buffers are settable to their enabled or disabled state by a bank enable command at the local buffer control. The enabled local buffers are configured to transfer local data to shift registers of their respective bank. The disabled local buffers are configured not to transfer the local data to the shift register of their respective bank.

Abstract: A comparator includes a second stage coupled between a first stage and a third stage. The second stage includes a first transistor coupled to be switched in response to a first output signal coupled to be received from the first stage. The first transistor is coupled generate a second output signal coupled to be received by the third stage. A second transistor is coupled to the first transistor. The first and second transistors are coupled between a first supply voltage and a reference voltage. A second stage current of the second stage is conducted through the first transistor and the second transistor. The second transistor is coupled to be switched in response to a third output signal coupled to be received from the third stage in response to the second output signal.

Abstract: The present disclosure provides a semiconductor device. The semiconductor device includes a semiconductor substrate and a first deep trench isolation (DTI) structure filled with a dielectric material formed on the semiconductor substrate. The first DTI structure is disposed in the first seal ring region and is extended into the semiconductor substrate. The semiconductor substrate has a pixel array region and a first seal ring region. The first seal ring region is proximate to an edge of the semiconductor substrate and surrounds the pixel array region. The first DTI structure is formed in the first seal ring region and surrounds the pixel array region.

Abstract: An image sensor has an array of pixels, each pixel having an associated shutter transistor coupled to transfer a charge dependent on light exposure of the pixel onto an image storage capacitor, the image-storage capacitors being configured to be read into an analog to digital converter. The shutter transistors are P-type transistors in N-wells, the wells held at an analog power voltage to reduce sensitivity of pixels to dark current; in an alternative embodiment the shutter transistors are N-type transistors in P-wells, the wells held at an analog ground voltage.

Abstract: A flip-chip sample imaging device with self-aligning lid includes an image sensor chip, a fan-out substrate, and a lid. The image sensor chip includes (a) a pixel array sensitive to light incident on a first side of the image sensor chip and (b) first electrical contacts disposed on the first side and electrically connected to the pixel array. The fan-out substrate is disposed on the first side, is electrically connected to the first electrical contacts, forms an aperture over the pixel array to partly define a sample chamber over the pixel array, and forms a first surface facing away from the first side. The lid is disposed on the first surface of the fan-out substrate, facing away from the first side, to further define the chamber. The lid includes an inner portion protruding into the aperture to align the lid relative to the fan-out substrate.

Abstract: A subrange analog-to-digital converter (ADC) converts analog image signal received from a bitline to a digital signal through an ADC comparator. The comparator is shared by a successive approximation register (SAR) ADC coupled to provide M upper output bits (UOB) of the subrange ADC and a ramp ADC coupled to provide N lower output bits (LOB). The digital-to-analog converter (DAC) of the SAR ADC comprises M buffered bit capacitors connected to the comparator. Each buffered bit capacitor comprises a bit capacitor, a bit buffer, and a bit switch controlled by one of the UOB of the SAR ADC. A ramp buffer is coupled between a ramp generator and a ramp capacitor. The ramp capacitor is further coupled to the same comparator. The implementation of ramp buffer and the bit buffers as well as their sharing of the same kind of buffer reduces differential nonlinear (DNL) error of the subrange ADC.

Abstract: A LCOS display panel comprises a silicon substrate, a pixel structure on the silicon substrate, a first and a second PI (polyimide) layers, a LC (liquid crystal) layer between the first and the second PI layers, wherein the second PI layer is disposed on the pixel structure, and the LC layer is disposed on the second PI layer, a glass substrate, an ITO (indium tin oxide) layer, a dam sealing a perimeter of the LCOS display panel to enclose the LC layer within the dam, wherein the dam is disposed between the first and second PI layers, and holds the silicon substrate and the glass substrate together, and a UV (ultra violet) cut filter in an active area of the LCOS display panel, wherein the active area of the LCOS display panel includes the LC layer and the pixel structure.

Abstract: A pixel array is provided that addresses leaking current at or near the floating diffusion region of the pixel cells. The pixel array includes an arrangement of trench isolation structures, including both front side deep trench isolation structure and front side shallow trench isolation structure that isolate the transistor channel regions from the pixel regions (e.g., photodiodes) of the pixel array. Example embodiments also include deep (N) doped wells that extend beneath the pixel transistor regions in order to “float” the P-well regions of the pixel transistor regions.

Abstract: A digital differential line receiver includes a differential signal to single-ended conversion amplifier coupled to receive a data line and data-complement line of a differential signal; a first termination resistor coupled to the data line of the differential signal; a second termination resistor coupled to the data-complement line of the differential signal; a first impedance-adjusting transistor coupled between the first termination resistor and a common mode line; a second impedance-adjusting transistor coupled between the second termination resistor and the common mode line; a control-voltage generator coupled to sense the common mode line and provide a control voltage, the control voltage generator configured to adjust the control voltage to a voltage level such that a combined impedance of the first termination resistor, the first impedance-adjusting transistor, the second termination resistor, and the second impedance-adjusting transistor matches a specified impedance.