Abstract: A LCOS display panel comprises a silicon substrate, a pixel structure on the silicon substrate, a first and a second PI (polyimide) layers, a LC (liquid crystal) layer between the first and the second PI layers, wherein the second PI layer is disposed on the pixel structure, and the LC layer is disposed on the second PI layer, a glass substrate, an ITO (indium tin oxide) layer, a dam sealing a perimeter of the LCOS display panel to enclose the LC layer within the dam, wherein the dam is disposed between the first and second PI layers, and holds the silicon substrate and the glass substrate together, and a UV (ultra violet) cut filter in an active area of the LCOS display panel, wherein the active area of the LCOS display panel includes the LC layer and the pixel structure.

Abstract: A pixel array is provided that addresses leaking current at or near the floating diffusion region of the pixel cells. The pixel array includes an arrangement of trench isolation structures, including both front side deep trench isolation structure and front side shallow trench isolation structure that isolate the transistor channel regions from the pixel regions (e.g., photodiodes) of the pixel array. Example embodiments also include deep (N) doped wells that extend beneath the pixel transistor regions in order to “float” the P-well regions of the pixel transistor regions.

Abstract: A digital differential line receiver includes a differential signal to single-ended conversion amplifier coupled to receive a data line and data-complement line of a differential signal; a first termination resistor coupled to the data line of the differential signal; a second termination resistor coupled to the data-complement line of the differential signal; a first impedance-adjusting transistor coupled between the first termination resistor and a common mode line; a second impedance-adjusting transistor coupled between the second termination resistor and the common mode line; a control-voltage generator coupled to sense the common mode line and provide a control voltage, the control voltage generator configured to adjust the control voltage to a voltage level such that a combined impedance of the first termination resistor, the first impedance-adjusting transistor, the second termination resistor, and the second impedance-adjusting transistor matches a specified impedance.

Abstract: A threshold detection circuit includes a plurality of capacitors. A plurality of switching circuits is coupled to the capacitors such that a first end of each of the capacitors is coupled to a corresponding photon sensor during detection intervals, and the first end of each capacitor is coupled to a variable initialization value during reset intervals. A threshold number of the capacitors are initialized to a first value and the remaining capacitors are initialized to a second value during reset intervals. A comparator is coupled to a second of the capacitors to generate a detection event in response to the threshold number of photon sensors sensing one or more incident photons during detection intervals.

Abstract: A low-power image capture device includes a first image buffer in SRAM coupled to receive images from an image sensor, and a second image buffer receiving images transferred in bursts from the first image buffer, the second image buffer implemented in PASR DRAM, the image buffers together operating as a first-in, first-out, (FIFO) buffer. The device includes an activation detector. The PASR DRAM is powered while receiving bursts of images from the first image buffer, and when the image capture device is in the activated mode; and in ultra-low power PASR mode otherwise. A method includes capturing images into the first image buffer, transferring the images in bursts into a second image buffer in PASR DRAM powered while receiving the images in bursts, the PASR DRAM otherwise in ultra-low power PASR mode; and, upon activating, an image processor receiving images from the second image buffer.

Abstract: A novel endoscope includes a camera module, an electrical cable, and an electrical connector. The camera module includes an analog image signal output terminal. The cable includes an analog image signal line having a first end connected to the analog image signal output terminal of the camera module. The electrical connector includes a set of electrical contacts configured to engage a complimentary set of electrical contacts of a host system. The set of electrical contacts includes at least an analog image signal contact connected to a second end of the analog image signal line of the cable.

Abstract: An image sensor chip-scale package includes a pixel array, a cover glass covering the pixel array, a dam, and an adhesive layer. The pixel array is embedded in a substrate top-surface of a semiconductor substrate. The semiconductor substrate includes a plurality of conductive pads in a peripheral region of the semiconductor substrate surrounding the pixel array. The dam at least partially surrounds the pixel array and is located (i) between the cover glass and the semiconductor substrate, and (ii) on a region of the substrate top-surface between the pixel array and the plurality of conductive pads. The adhesive layer is (i) located between the cover glass and the semiconductor substrate, (ii) at least partially surrounding the dam, and (iii) configured to adhere the cover glass to the semiconductor substrate.

Abstract: An image sensor comprises a pixel array of pixel cells. A pixel cell comprises a photodiode, a reset transistor, a transfer transistor, at least one source follower transistor, a sample and hold circuit, an active reset transistor, and a readout transistor. A readout circuitry reads out image data from each columns of pixel cells. A column differential amplifier in the readout circuitry feeds back a column reset drive voltage to each pixel cells arranged in the same column. Signal data of each pixel cells in the same column are read out globally when all the active reset transistors are switched off. Determined by switching configurations of each active reset transistors of pixel cells in the same column, noise data of each pixel cells in the same column are read out either globally or row-by-row. Final image data is achieved by applying the method of correlated double sampling (CDS).

Abstract: An image sensor includes a two-dimensional photodiode-array formed in a semiconductor substrate, a first waveguide, and a first color filter. The first waveguide is aligned to a first photodiode of the photodiode-array, located above a top substrate surface of the semiconductor substrate. A first core of the first waveguide has a first core width that is less than a pitch of the photodiode-array in a first direction and a second direction corresponding to respective orthogonal dimensions of the photodiode-array. The first color filter is on a top waveguide surface of the first waveguide and has a first non-uniform thickness above the first core. The first waveguide is between the top substrate surface and the first color filter.

Abstract: A pixel cell includes an electrically conductive tunnel contact formed across a surface of a source follower gate, the tunnel contact having a first end, a second end, and an intermediate portion between the first and second ends. The first end is coupled to a floating diffusion FD, the second end is coupled to the first doped region of a reset transistor RST. The tunnel contact is formed in physical and in electrical contact with the surface of the source follower gate for a length of the intermediate portion substantially equal to a width of the source follower gate. Methods of forming the pixel cell are also described.

Abstract: Image sensor includes a first semiconductor material and a plurality of first doped regions disposed in the semiconductor material. The plurality of first doped regions is part of a plurality of photodiodes to receive light and convert the light into image charge. A second semiconductor material is disposed on the first semiconductor material, and a plurality of second doped regions is disposed in the second semiconductor. The plurality of second doped regions is electrically coupled to the plurality of first doped regions, and the plurality of second doped regions is part of the plurality of photodiodes.

Abstract: A readout circuit for use in an image sensor includes a first sample and hold (SH) circuit coupled to a bitline that is coupled to a pixel array. A second SH circuit is coupled to the bitline. A bypass switch is coupled to the bitline, the first SH circuit, and the second SH circuit. An analog to digital converter (ADC) is coupled to the bypass switch. The bypass switch is configured to provide an image charge value from the pixel array to the ADC through the bitline, or through one of the first SH circuit or the second SH circuit in response to a switch select signal.

Abstract: Image sensors include a photodiode disposed in a semiconductor substrate and a transistor operatively coupled to the photodiode. At least three substrate trench structures are formed in the semiconductor substrate, defining two nonplanar structures, each having a plurality of sidewall portions. An isolation layer includes at least three isolation layer trench structures, each being disposed in a respective one of the three substrate trench structures. A gate includes three fingers, each being disposed in a respective one of the three isolation layer trench structures. An electron channel of the transistor extends along the plurality of sidewall portions of the two nonplanar structures in a channel width plane.

Abstract: Image sensors include a photodiode disposed in a semiconductor substrate and a transistor operatively coupled to the photodiode. The transistor includes a nonplanar structure disposed in the semiconductor substrate, which is bounded by two outer trench structures formed in the semiconductor substrate. Isolation deposits are disposed within the two outer trench structures formed in the semiconductor substrate. A gate includes a planar gate and two fingers extending into one of two inner trench structures formed in the semiconductor substrate between the nonplanar structure and a respective one of the two outer trench structures. This structure creates an electron channel extending along a plurality of sidewall portions of the nonplanar structure in a channel width plane.

Abstract: A low-height projector assembly includes a biconvex lens, a converging lens, an aperture stop, and a beam-steerer between the biconvex lens and the converging lens. The biconvex lens has a principal plane, a focal length, and a first optical axis. The converging lens has a second optical axis laterally offset from the first. The beam-steerer is configured to steer light from the biconvex lens to the converging lens. An aperture-stop plane intersects the second optical axis and the aperture stop. On the second optical axis, at least one of a front surface and a back surface of the converging lens is between the aperture-stop plane and the beam-steerer. The axial chief ray's propagation distance from the principal plane to the aperture stop differs from the focal length by less than half the depth of focus of the biconvex lens.

Abstract: An analog to digital conversion (ADC) circuit includes a ramp circuit coupled to output a ramp signal, and the ramp signal is offset from a starting voltage by an offset voltage. The ramp signal ramps towards the starting voltage. A counter circuit is coupled to the ramp circuit to start counting after the ramp signal returns to the starting voltage, and a comparator is coupled to the counter circuit and a bitline to compare the ramp signal to a pixel signal voltage on the bitline. In response to the ramp signal equaling the pixel signal voltage, the comparator stops the counter.

Abstract: A method for manufacturing an image sensor includes, for each of a plurality of photosensitive pixels of the image sensor, forming a trench in a semiconductor substrate of the image sensor, and depositing temporary transfer gate material in and above the trench. The method further includes, after the step of depositing temporary transfer gate material, high-temperature annealing at least a portion of the semiconductor substrate. In addition, the method includes, after the step of high-temperature annealing, (a) removing the temporary transfer gate material, thereby reopening the trench, (b) depositing a passivation lining, having a high-k dielectric, in the reopened trench, and (c) depositing metal on the high-k dielectric passivation lining to form a metal vertical transfer gate in the trench and extending above the trench.

Abstract: A time-of-flight (TOF) sensor includes a light source, a plurality of avalanche photodiodes, and a plurality of pulse generators. Control circuitry is coupled to the light source, the plurality of avalanche photodiodes, and the plurality of pulse generators, and the control circuitry includes logic that when executed by the control circuitry causes the time-of-flight sensor to perform operations. The operations include emitting the light from the light source, and receiving the light reflected from an object with the plurality of avalanche photodiodes. A plurality of pulses is output from the individual pulse generators corresponding to the individual avalanche photodiodes that received the light, and a timing signal is output when the plurality of pulses overlap temporally. A time is calculated when a first avalanche photodiode in the plurality of avalanche photodiodes received the light.

Abstract: A test voltage sample and hold circuitry is disclosed in a readout circuitry of an image sensor. This circuitry samples a voltage at demand value based on a ramp voltage shared by the ADC comparators of the readout circuitry. The value of the sampled voltage is controlled by a control circuitry which is able to predict and calculate at what time a ramp generator may carry the demand voltage value. The sampled voltage is held by a hold capacitor during readout of one row and is accessed during the next row by the control circuitry as test data to drive a device under test (DUT) which may be any portion of the image sensor to be tested. Measured data out of the DUT is compared with expected data. Based on the result of the comparison, a signal indicates the pass or fail of the self-test concludes a self-test of the DUT.

Abstract: A cavityless chip-scale image-sensor package includes a substrate, a microlens array, and a low-index layer. The substrate includes a plurality of pixels forming a pixel array. The microlens array includes a plurality of microlenses each (i) having a lens refractive index, (ii) being aligned to a respective one of the plurality of pixels and (iii) having a non-planar microlens surfaces facing away from the respective one of the plurality of pixels. The low-index layer has a first refractive index less than the lens refractive index. The low-index layer also includes a bottom surface, at least part of which is conformal to each non-planar microlens surface. The microlens array is between the pixel array and the low-index layer.