Abstract: An optical fingerprint sensor with spoof detection using polarization includes a plurality of lenses; an image sensor including a pixel array that includes a plurality of first photodiodes; a line between a center of a light-sensitive surface of each first photodiode and an optical center of each lens forms an optical axis of a plurality of optical axes; at least one apertured baffle-layer positioned between the image sensor and the plurality of lenses and each having a respective plurality of aperture stops, each aperture stop being center-aligned with the optical axis; a plurality of second photodiodes intercalated with the plurality of first photodiodes, wherein each second photodiode is configured to detect light having passed through lens and at least one aperture stop not aligned along optical axis; and at least one polarizing element positioned to polarize electromagnetic energy impinging the plurality of second photodiodes.

Abstract: An imaging device includes a pixel array including pixel circuits arranged into rows and columns. Each bitline of a plurality of bitlines is coupled to a respective column of pixel circuits of the pixel array. The plurality of bitlines is grouped into pairs of bitlines. A plurality of binning circuits is coupled to the plurality of bitlines. Each binning circuit is coupled to a respective pair of bitlines and is responsive to a multi-mode select signal. Each binning circuit is configured to output a binned signal responsive to the first and second bitlines of the respective bitline pair in a first mode. Each binning circuit is configured to output a first signal from a first bitline of the respective bitline pair in a second mode. Each binning circuit is configured to output a second signal from the second bitline of the respective bitline pair in a third mode.

Abstract: A liquid crystal on silicon device is described. The liquid crystal on silicon device includes a plurality of mirror electrodes, a transparent electrode, a liquid crystal material, and a plurality of microlenses. The plurality of mirror electrodes are arranged periodically to form an array of pixels, each pixel included in the array of pixels configurable to reflect incident light. The transparent electrode is optically aligned with the plurality of mirror electrodes. The liquid crystal material is disposed between the transparent electrode and the plurality of mirror electrodes. The plurality of microlenses are optically aligned with the plurality of mirror electrodes. Each microlens included in the plurality of microlenses is positioned to focus the incident light on a respective one of the plurality of mirror electrodes.

Abstract: An image sensor includes photodiodes disposed in a pixel region and proximate to a front side of a semiconductor layer. A backside metal grating is formed in a backside oxide layer disposed proximate to a backside of the semiconductor layer. A deep trench isolation (DTI) structure with a plurality of pixel region portions and an edge region portion is formed in the semiconductor layer. The pixel region portions are disposed in the pixel region of the semiconductor layer such that incident light is directed through the backside metal grating, through the backside of the semiconductor layer, and between the pixel region portions of the DTI structure to the photodiodes. The edge region portion of the DTI structure is disposed in an edge region outside of the pixel region. The edge region portion of the DTI structure is biased with a DTI bias voltage.

Abstract: An endoscope comprises a light splitting device for transmitting a first illuminating light and reflecting a second illuminating light emitted by a light source. The first illuminating light passes through a first color filter transmitting a first color. The second illuminating light passes through the second color filter transmitting a second color. The first color is different from the second color. The light splitting device combines a first incident light of the first color and a second incident light of the second color. The first incident light of the first color and the second incident light of the second color pass through an imaging lens and form images of the first color and the second color on an image sensor, respectively. A CFA (color filter array) comprising a plurality of first CFA components of the first color and a plurality of second CFA component of the second color covering the image sensor.

Abstract: A flare-blocking image sensor includes large pixels and small pixels, a microlens, and an opaque element. The large pixels and small pixels form a first and second pixel array respectively, each having a pixel pitch Px and Py. The second pixel array is offset from the first pixel array by ½Px and ½Py. A first large pixel of the large pixels is between and collinear with a first and a second small pixel separated by ?{square root over (Px2+Py2 )} in a first direction and each having a width W less than both pixel pitch Px and Py. The microlens is aligned with the first large pixel. The opaque element is between the first large pixel and the microlens and extends, in the first direction, less than ½(?{square root over (Px2+Py2)}?W) from the first small pixel toward the second small pixel. The opaque element has a width perpendicular to the first direction not exceeding width W.

Abstract: An imaging device includes pixel circuits that include either image sensing photodiodes or phase detection autofocus (PDAF) photodiodes. The PDAF photodiodes are included in a first PDAF pixel circuit included in a first grouping of rows, and a second PDAF pixel circuit included in a second grouping of rows of a pixel array. Bitline pairs are coupled to respective columns of the pixel array. Each bitline pair includes a first bitline coupled to the first grouping of rows and a second bitline coupled to the second grouping of rows of respective columns of the pixel array. Multiplexers are configured to select one of respective first or second bitlines of each bitline pair. A PDAF multiplexer is coupled to a PDAF select signal and the second PDAF circuit through a respective bitline pair. The remaining multiplexers are coupled to a select signal and are coupled to remaining bitline pairs.

Abstract: An imaging device includes a photodiode array with a first and second photodiodes. First and second floating diffusions are configured to receive charge from the first and second photodiodes, respectively. An analog to digital converter (ADC) is configured to receive simultaneously first and second bitline signals from the first and second floating diffusions, respectively. The ADC is configured to generate a reference readout in response to the first and second bitline signals after a reset operation. The ADC next generates a first half of a phase detection autofocus (PDAF) readout in response to the first and second bitline signals after charge is transferred from the first PDAF photodiode to the first floating diffusion. The ADC then generates a full image readout in response to the first and second bitline signals after charge is transferred from the second photodiode to the second floating diffusion.

Abstract: A method for forming a transfer gate includes (i) forming a dielectric pillar on a surface of a semiconductor substrate and (ii) growing an epitaxial layer on the semiconductor substrate and surrounding the dielectric pillar. The dielectric pillar has a pillar height that exceeds an epitaxial-layer height of the epitaxial layer relative to the surface. The method also includes removing the dielectric pillar to yield a trench in the epitaxial layer. A pixel includes a doped semiconductor substrate having a front surface opposite a back surface. The front surface forms a trench extending a depth zT with respect to the front surface within the doped semiconductor substrate along a direction z perpendicular to the front surface and the back surface. The pixel has a dopant concentration profile, a derivative thereof with respect to direction z being discontinuous at depth zT.

Abstract: Image sensors include a pixel die that is stacked on a logic die. The logic die includes at least one function logic element disposed on a bond side thereof, and a logic oxide array of raised logic oxide features also disposed on the bond side. The pixel die includes a pixel array disposed on a light receiving side thereof, and a pixel oxide array of raised pixel oxide features disposed on a bond side of the pixel die. A plurality of outer bonds is disposed between an outer region of the logic die and an outer region of the pixel die. A plurality of inner bonds is formed at an inner region of the image sensor between the pixel oxide array and the logic oxide array, the inner bonds being spaced apart by a plurality of fluidly connected air gaps that extend between the logic die and the pixel die.

Abstract: A pixel includes an array of a plurality of photodiodes. The array of photodiodes includes a plurality of rows of photodiodes and a plurality of columns of photodiodes. The plurality of photodiodes includes a set of first photodiodes that has a first surface area and at least one second photodiode that has a second surface area that is smaller than the first surface area. The first photodiodes are arranged to be symmetric with respect to the at least one second photodiode. Output circuitry is electrically coupled to each of the first photodiodes in the set of first photodiodes. A switch is selectively, operably closed to electrically couple the output circuitry to the second photodiode.

Abstract: A pixel circuit includes a photodiode and a floating diffusion disposed in a semiconductor substrate. A transfer gate is disposed between the photodiode and the floating diffusion to transfer photogenerated image charge from the photodiode to the floating diffusion. A dual floating diffusion (DFD) transistor is coupled between the floating diffusion and a DFD capacitor. The DFD transistor includes a DFD gate that includes a planar gate portion disposed over a surface of the semiconductor substrate and a vertical gate portion that extends vertically from the planar gate portion into the semiconductor substrate. The vertical gate portion of the DFD gate is configured to increase a gate to substrate coupling capacitance of the DFD transistor. The gate to substrate coupling capacitance and the DFD capacitor are coupled to increase an effective capacitance associated with the floating diffusion in response to the DFD transistor being turned on.

Abstract: A method of compressing and storing preview video includes performing colorspace-reduction image compression on a reference frame of a video to generate a colorspace-reduced reference frame; determining difference blocks representing areas of a subsequent image frame that differ from the reference frame and generating a difference frame comprising colorspace-reduced image data of the difference blocks; generating a video stream comprising a color palette, the colorspace-reduced reference frame, and the difference frame, and storing the video stream in an extreme low-voltage memory; and injecting, into the video stream prior to storing the video stream in the extreme low-voltage memory, a plurality of resynchronization codes for each reference frame and a plurality of resynchronization codes for each difference frame, the resynchronization codes comprising a byte sequence unique to resynchronization codes.

Abstract: Examples of the disclosed subject matter propose disposing deep trench isolation structure around the perimeter of the pixel transistor region of the pixel cell. In some example embodiments, the deep trench isolation structure extends into the semiconductor substrate from the back side of the semiconductor substrate and abuts against or contacts the bottom of shallow trench isolation structure disposed in the front side of the semiconductor substrate. Together, the trench isolating structure isolates the transistor channel of the pixel transistor region. The formation and arrangement of the trench isolation structure in the pixel transistor region forms a floating doped well region, such as a floating P-doped well region (P-well), containing a floating diffusion (FD) and source/drains (e.g., (N) doped regions) of the pixel transistors. This floating P-well region aims to reduce junction leakage associated with the floating diffusion region of the pixel cell.

Abstract: A time-of-flight (TOF) pixel includes a semiconductor material and a photogate disposed proximate to a frontside of the semiconductor material. The photogate is positioned to transfer charge in the semiconductor material toward the frontside in response to a voltage applied to the photogate. A floating diffusion is disposed in the semiconductor material proximate to the frontside of the semiconductor material, and one or more virtual phase implants is disposed in the semiconductor material proximate to the frontside of the semiconductor material. At least one of the one or more virtual phase implants extend laterally from under the photogate to the floating diffusion to transfer the charge to the floating diffusion.

Abstract: A readout circuit for use in an image sensor includes a plurality of comparators. Each one of the plurality of comparators is coupled to receive a ramp signal and a respective analog image data signal from a respective one of a plurality of column bit lines to generate a respective comparator output. Each one of a plurality of arithmetic logic units (ALUs) is coupled to receive phase-aligned Gray code (GC) outputs generated by a GC generator. Each one of the plurality of ALUs is further coupled to a respective one of the plurality of comparators to receive the respective comparator output. Each one of the plurality of ALUs is coupled to latch the phase-aligned GC outputs in response to the respective comparator output to generate a respective digital image data signal.

Abstract: A clock control circuit of an ADC includes a plurality of fractional divider circuits, each including a programmable integer divider coupled to receive an enable skew signal, a clock signal, and an output integer signal to divide down the clock signal by a factor responsive to the output integer signal to generate a fractional divider signal. A delta-sigma modulator is coupled to receive a fractional modulus signal, an input integer signal, and the fractional divider signal to generate the output integer signal, which is a varying signal each cycle and having a long term average DC value substantially equal to a fractional divider ratio K. An extended gain control circuit is coupled to receive the fractional divider signal from each of the fractional divider circuits to generate a plurality of ramp clock signals with adjustable frequencies to adjust a gain setting of a ramp generator of the ADC.

Abstract: An event driven sensor includes an arrangement of photodiodes including an inner portion laterally surrounded by an outer portion. An outer pixel cell circuit is coupled to generate an outer pixel value in response to photocurrent generated by the outer portion. The outer pixel value is a binned signal representative of an average value of brightness of incident light on the arrangement of photodiodes. An inner pixel cell circuit is coupled to the inner portion to generate an inner pixel value in response to photocurrent generated by from the inner portion. An event driven circuit is coupled to the outer pixel cell circuit and the inner pixel cell circuit. The event driven circuit is coupled to generate an output signal responsive to an inner brightness indicated by the inner pixel value relative to an outer brightness indicated by the outer pixel value.

Abstract: A CMOS image sensor has an array of photodiode cells, the photodiode cells each include four buried photodiodes coupled by vertical transfer gate transistors to a single floating node diffusion. Each cell also has a reset transistor coupled to the floating node diffusion, a source follower transistor having gate coupled to the floating node diffusion, and a read select transistor coupled to the source follower transistor. The reset transistor, source follower transistor, and read select transistor have predominately gate and shape edges oriented at an angle greater than 30-degrees and less than 60-degrees from a line extending along an entire horizontal row of photodiodes of a photodiode array of the image sensor and are formed vertically above, and in the same integrated circuit as, the photodiodes of the photodiode array.

Abstract: An image sensor includes a photodiode array and a color filter array optically aligned with the photodiode array. The photodiode array includes a plurality of photodiodes disposed within respective portions of a semiconductor material. The color filter array includes a plurality of color filters arranged to form a plurality of tiled minimal repeating units. Each minimal repeating unit includes at least a first color filter with a red spectral photoresponse, a second color filter with a yellow spectral photoresponse, and a third color filter with a panchromatic spectral photoresponse.